Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1996-08-28
2001-10-30
Wu, Xiao (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S211000
Reexamination Certificate
active
06310599
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an apparatus and method for protecting LCD panels from damage during manufacturing, development, and operation. The present invention has particular application to passive and active matrix monochrome and color flat panel displays.
BACKGROUND OF THE INVENTION
Flat panels displays are known for use with computer systems, particularly laptop or portable computers and the like. Such flat panel displays may also be applied to other types of devices such as televisions or television monitors, industrial and automotive controls and the like. LCD panels are particularly popular for use in panel displays due to their relatively low cost and high resolution.
LCD panels use a layer of liquid crystal material portions of which may be controllably aligned in particular directions using a bias voltage. Polarized light may pass through portions of the liquid crystal or be reflected, depending upon bias voltage application (and liquid crystal alignment) at a particular portion. Signals provided by a passive or active matrix may thus twist portions of the LCD crystal to generate display elements.
The liquid crystal display has a structure similar to a capacitor in that an insulator (liquid crystal) may be provided between two electrodes (bias voltage lines). The bias voltage may be provided with an AC component to prevent breakdown of the liquid crystal over time. If the bias voltage is not provided with such an AC component, electrolysis may occur within the liquid crystal display, and the liquid crystal may segregate and breakdown, causing permanent damage to the liquid crystal display.
LCD panels may also be damaged in other ways. For example, voltage or current drivers provided within an LCD display device to provide bias voltages may be overdriven to a point where an individual LCD driver may be damaged.
Such damage may result in all or portions of an LCD display being disabled. For example, if an individual line driver is damaged within an LCD panel, a corresponding line may not be driven, resulting in a missing line or stripe is appearing in the LCD display.
Such damage may occur to an LCD panel if an LCD display is operated without proper clock (e.g., frame clock, line clock, pixel clock, or the like) or control signals. Power and clock signals to an LCD display may be applied and removed in a particular order and fashion in order to prevent damage to the panel.
FIG. 1
is a waveform diagram illustrating the order in which clock and power signals may be applied to and removed from an LCD panel in order to prevent damage to a panel.
As illustrated in
FIG. 1
, power control signal GR
1
may first be asserted to an LCD panel. Next, LCD timing signals (e.g., line clock, frame clock, pixel clock) may be applied to a panel. Third, a power control signal GR
2
may be applied to an LCD panel. Power control signals GR
1
and GR
2
may represent reference voltages (e.g., positive and negative) used to generate an AC bias signal to the flat panel display.
When these power and clock signals have been applied in this order, an LCD panel may be successfully power up without damage. To power down an LCD panel, the power and clock signals may be removed in a reverse order. Relative timings t1, t2, t3, and t4, between application of the various signals may be specified by a panel manufacturer to prevent malfunction and/or damage to the panel.
FIG. 2
is a simplified block diagram illustrating the connection of flat panel display timing signal lines from a display controller
250
to a flat panel display
201
. Signal lines
202
,
203
, and
204
transmit clock signals LFS, LLCLK, and SCLK, respectively. Signal LFS is a clock signal indicating field timing for a display image. Signal LLCLK is a line clock signal for a display image, while SCLK is a pixel clock signal for a display image.
Signal lines
202
,
203
, and
204
may pass through pad drivers
210
,
209
, and
208
, respectively to output pads
207
,
206
, and
205
, respectively, of display controller
250
. Such pad drivers and output pads are known in the semiconductor art. In the prior art, an output-only pad (i.e. a pad driven only by an output pad driver) may have been used with such clock signals, as such clock signal lines
202
,
203
, and
204
are generally output-only lines.
Under normal operation, it may be somewhat difficult; for a situation to arise where an LCD panel may be damaged due to normal inputs from a display controller. However with the advent of more sophisticated operating systems software (e.g., Window™ 95, O/S 2™ or the like) situations may arise where proper clock or control signal may not be generated, particularly if a user incorrectly configures a computer system (e.g., changing mode incorrectly).
In addition, such situations may arise when a component within a computer system malfunctions. For example, if a display controller IC or other component driving a flat panel display fails in whole or part, the flat panel display may also fail if control or clock signals are distorted or cut off in a particular manner. For example, if clock signals to a flat panel display are terminated while power control signals remain applied, damage to the current or voltage supplies within the panel may occur.
Moreover, when developing and testing new computer systems, it may be necessary to test new components (e.g., display controllers or the like) with actual flat panel displays. In addition, during manufacture of computer systems (e.g., laptop computer or the like) it may be necessary to power up new systems to check components (e.g., burn-in or the like). During such testing and/or burn-in, improper clocking signals and/or control signals may be generated or may be missing for the flat panel controller. In a relatively short period of time (e.g., seconds or less) a flat panel display may be partially or totally destroyed, if such clocking and/or control signals are missing or improper. Damage to bias voltage drivers may occur within milliseconds, whereas damage to crystals within an LCD display may take longer.
If a particular development or manufacturing problem is encountered numerous times, a number of flat panel displays may be destroyed before the problem can be corrected. The cost of such destroyed displays may significantly increase the cost of development of computer components and/or the cost of manufacturing new computers. Thus, it remains a requirement in the art to provide a means for protecting flat panel displays from incorrect or missing timing signals in order to prevent damage or destruction of such displays.
SUMMARY OF THE INVENTION
A flat panel display controller includes an output driver for outputting a clock signal to a flat panel display. A corresponding input driver, coupled to the output driver, feeds back the clock signal to the flat panel display controller.
In the preferred embodiment, the output of input pad driver serves to reset a counter, which otherwise counts freely from a time base. The time base may be independently generated off-chip with a frequency depending upon which signal is to be monitored. If the counter overflows, a carry signal is output to a flat panel power control sequence circuit to shut down power to flat panel display before damage occurs.
In a second embodiment, an edge detecting circuit, coupled to the input driver, detects edge transitions in the clock signal and outputs a pulse when an edge transition is detected.
The output of the edge detecting circuit is fed to a MUX which is driven by a window signal to MUX the output of the edge detecting circuit with a divided value of the edge detection circuit in order to compensate for horizontal and vertical retrace periods. The output: of the MUX resets a counter which is clocked by an independent time base. If the counter overflows, a carry signal is output to a flat panel power control sequence circuit to shut down power to flat panel display before damage occurs.
REFERENCES:
patent: 4827347 (1989-05-01), Bell
patent: 4845482 (1989-07-01), Howard et al.
paten
Bril Vlad
Eglit Alexander Julian
Han Robin Sungsoo
Jammula Muralidhar Reddy
Bell Robert A.
Cirrus Logic Inc.
Lin Steven
Wu Xiao
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