Multiplex communications – Diagnostic testing – Fault detection
Reexamination Certificate
1999-10-14
2003-10-28
Chin, Wellington (Department: 2664)
Multiplex communications
Diagnostic testing
Fault detection
C370S216000, C370S395600
Reexamination Certificate
active
06639899
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to asynchronous transfer mode (ATM) networks. The invention relates more specifically to the detection of errors in ATM cell payloads within telecommunication devices. Various aspects of the invention provide methods for detecting errors in ATM cell payloads, an ATM switch adapted to detect errors in ATM cell payloads, and a signal useful in detecting errors in ATM cell payloads.
BACKGROUND
In an ATM network, data is forwarded in equal length cells. Each cell includes a header, which includes information specifying the destination of the cell, and a data payload. According to the current ATM specification, each ATM cell is 53 bytes long and consists of a 48-byte payload and a 5-byte header.
In an ATM network a number of virtual circuit connections (VCCs) are set up between pairs of end points on the network. Streams of ATM cells can be sent along each virtual circuit connection. In passing along a virtual circuit connection, each ATM cell typically passes through one or more ATM switches. The ATM switches direct the cells so that each cell will arrive at its intended end point. A challenge facing the designers of ATM networks is the very high speeds at which ATM cells must be passed through the network and switched by network switches. ATM cells can become corrupted as they pass through an ATM network for various reasons including hardware faults, hardware failures, and software errors which might, for example, cause certain components within an ATM switch to be improperly configured.
There are many systems for measuring the end-to-end performance of connections provided by an ATM network. Such systems typically measure the performance of end-to-end channels across an ATM network. While there are methods for determining the node in an ATM network at which faults are occurring, such methods do not facilitate the location of specific faulty cards or modules of telecommunication devices on the ATM network. In studying the source of errors in ATM networks it is often assumed that errors arise in the communication links connecting switches in the network and that network switches perfectly transmit all ATM cells which they receive. It is inevitable, however, that some ATM cells will become corrupted as they pass through ATM switches. Since ATM cells pass through many switches in traversing most practical ATM networks, the localization of intermittent errors to particular switches or to particular portions of switches can be very difficult with prior methods.
Most standards governing the manner in which ATM cells are passed over the physical links which connect telecommunication devices in ATM networks include error detection protocols. There are no such standards for detecting ATM cells which become corrupted within telecommunication devices.
There is a need for an effective way to detect and localize errors which result in the corruption of data payloads in ATM cells. In particular, there is a need for effective methods and apparatus capable of identifying specific cards or modules within ATM telecommunication devices at which ATM cells are being corrupted. There is a particular need for such methods and apparatus which fully cover data paths within ATM telecommunication devices and do not merely cover specific interfaces between devices or functions internal to a telecommunication device, such as a switch. Such data paths may include several buffers, interfaces, connections etc. as they pass through a telecommunication device.
SUMMARY OF INVENTION
This invention provides methods and apparatus for verifying the integrity of the data payloads of ATM cells within ATM telecommunication devices, such as ATM switches. The methods of the invention involve generating a payload integrity verification code for ATM cells entering a telecommunication device. The payload integrity verification code is attached to the cell. At one or more downstream locations within the telecommunications device the payload integrity verification code is checked to determine whether it matches the cell data payload. This may be done by recalculating the payload integrity verification code and comparing it to the originally calculated payload integrity verification code. Preferably the payload integrity verification code is checked at multiple downstream locations to permit the identification of defective modules within the telecommunication device.
In some embodiments of the invention the payload integrity verification code is written to the VPI/VCI fields of the cell (i.e. one or more of the 5th through 28th bits of the 5 byte ATM cell header). While an ATM cell is in transit through a telecommunication device the VPI field, the VCI field, or both the VPI AND VCI fields are often irrelevant. Therefore one can surprisingly provide cell payload integrity verification by including a payload integrity verification code in VPI field and/or the VCI field without adversely affecting throughput of the telecommunication device. The payload integrity verification code may be a checksum, a CRC-8 value, a CRC-4 value, a parity bit, a BIP code or another suitable error correction or error detection code. In other embodiments of the invention the payload integrity verification code is included in an additional header or trailer attached to an ATM cell.
Accordingly, one aspect of the invention provides a method for verifying the integrity of an ATM cell payload within an ATM telecommunication device. The method comprises: generating a first payload integrity verification code for the payload of an ATM cell at an upstream location within an ATM telecommunication device; attaching the first payload integrity verification code to the cell; reading the cell payload and the first payload integrity verification code from the cell at a downstream location and checking to see whether the cell payload matches the first payload integrity verification code as read from the cell. In some embodiments checking to see whether the cell payload matches the first payload integrity verification code comprises generating a second payload integrity verification code from the cell payload at a downstream location within the telecommunication device; comparing the second payload integrity verification code to the first payload integrity verification code attached to the cell; and, if the first and second payload integrity verification codes are not identical signalling an error condition.
Another aspect of the invention provides an ATM telecommunication device for use in an ATM packet switching network. The ATM telecommunication device comprises: an ingress, an egress, and a data path extending between the ingress and the egress; a payload integrity verification code calculator at a first location on the data path; a payload integrity verification code writing circuit connected to write a first payload integrity verification code to an ATM cell at the first location; and a payload integrity verification circuit at a second location on the data path downstream from the first location. In a preferred embodiment the payload integrity verification circuit comprises a second payload integrity verification code generator located on the data path downstream from the first location; and, a comparing circuit connected to compare the first payload integrity verification code generated by the first payload integrity verification code calculator to a second payload integrity verification code detection generated by the second payload integrity verification code calculator and a signalling circuit to generate an error signal whenever the first payload integrity verification code is different from the second payload integrity verification code.
Yet another aspect of the invention provides a signal propagating in an ATM switch. The signal comprises an ATM cell payload, an ATM cell header, and an payload integrity verification code for the ATM cell payload, the payload integrity verification code stored in VCI and/or VPI fields of the ATM header.
A further aspect of the invention comprises a method for passing in
Driediger Steve
Law Randall Allan
Margerm Steven Douglas
Morton Robert
Nadj Pual
Alcatel Canada Inc.
Chin Wellington
Fox Jamal A.
Oyen Wiggs Green & Mutala
LandOfFree
Method and apparatus for providing integral cell payload... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for providing integral cell payload..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for providing integral cell payload... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3113191