Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2002-05-20
2004-11-30
Deberadinis, Robert L (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S111000
Reexamination Certificate
active
06826025
ABSTRACT:
BACKGROUND OF THE INVENTION
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to electrostatic discharge (ESD) protection circuits and, more particularly, to ESD circuits as they relate to integrated circuits.
2. Description of the Related Art
As electronic components are getting smaller and smaller along with the internal structures in integrated circuits, it is getting easier to either completely destroy or otherwise impair electronic components. In particular, many integrated circuits are highly susceptible to damage from the discharge of static electricity. Electrostatic discharge (ESD) is the transfer of an electrostatic charge between bodies at different electrostatic potentials (voltages), caused by direct contact or induced by an electrostatic field. The discharge of static electricity, or ESD, has become a critical problem for the electronics industry.
Device failures that result from ESD events are not always immediately catastrophic or apparent. Often, the device is only slightly weakened but is less able to withstand normal operating stresses and, hence, may result in a reliability problem. Therefore, various ESD protection circuits must be included in the device to protect the various components.
The use of System-On-A-Chip (SOC) for various applications such as high-speed high-speed data rate transmission, optical interconnect, wireless and wired marketplaces has expanded exponentially. Each one of these applications has a wide range of power supply conditions, number of independent power domains, and circuit performance objectives. Typically, different power domains are established between digital, analog and radio frequency (RF) functional blocks on an integrated chip. With system-on-a-chip (SOC), different circuit and system functions are integrated into a common chip substrate.
The use of a common substrate, however, introduces additional noise and ESD problems. Various methods have been used to address these additional concerns. For example, it is common within the industry to separate circuits spatially to avoid noise interactions and/or provide structures in-between to avoid current flow. Another method is to separate the power supply and ground connections to a circuit function using separate pads (or pins).
In order to avoid noise coupling from one ground to another, the grounds of the circuit functional blocks are typically separated and at times decoupled from the chip substrate by wells, tubs, isolated epitaxial regions in the semiconductor chip and also by using independent electrical interconnects of vias, wires and power pads.
The above noted methods are most prevalent where digital, analog circuit, and Radio Frequency (RF) blocks are used on the same integrated circuit or SOC.
The methods of separating the power and ground domains from one another introduces new ESD concerns. ESD testing of such an integrated circuit should be performed between pin-to-rail, rail-to-rail and pin-to-pin. Furthermore, the following ESD rules must be observed: (1) the current introduced from an ESD event cannot flow from any pin of one power domain to any pin of a different power domain; and (2) similarly, current introduced by the ESD event can not flow from one power domain to a different power domain (either dependent or independent).
It would be advantageous, therefore, if an ESD circuit could be constructed to sufficiently to protect integrated circuits having a common substrate. It would be further advantageous if such an ESD circuit could be combined with a noise reduction circuit. The present invention provides such an ESD circuit.
BRIEF SUMMARY OF THE INVENTION
In one aspect, the present invention uses the inherent resistance of the substrate to trigger an ESD device for circuits having separate power and/or ground pins from one another.
In yet another aspect, the present invention enhances the inherent resistance of the substrate, and uses the enhanced resistance as a trigger for an ESD device.
In yet a further aspect, the present invention uses low noise devices to keep noise from being introduced into a circuit.
REFERENCES:
patent: 5290724 (1994-03-01), Leach
patent: 5416351 (1995-05-01), Ito et al.
patent: 5430595 (1995-07-01), Wagner et al.
patent: 5452171 (1995-09-01), Metz et al.
patent: 5475255 (1995-12-01), Joardar et al.
patent: 5717559 (1998-02-01), Narita
patent: 5754381 (1998-05-01), Ker
patent: 6049119 (2000-04-01), Smith
patent: 6268992 (2001-07-01), Lee et al.
patent: 0753892 (1997-01-01), None
patent: 6275787 (1994-09-01), None
Singh Raminderpal
Voldman Steven Howard
Benenson Boris
Deberadinis Robert L
Henkler Richard A.
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