Method and apparatus for providing electrostatic discharge prote

Details Method and apparatus for providing electrostatic discharge prote Method and apparatus for providing electrostatic discharge prote

1996-10-01

1999-03-02

Medley, Sally C.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 91, H02H 900

Patent

active

058779272

ABSTRACT:
An arrangement for preventing damage to a circuit of an integrated circuit chip due to the occurrence of voltage introduced externally to the integrated circuit is disclosed. The arrangement generally has a timer circuit, a clamping circuit, and an override circuit. The clamping circuit is coupled between an input and ground such that voltages and currents applied to the input are shunted to ground for a first length of time. The timer circuit is coupled to the input and passes a voltage applied to the input for the first length of time. The output of the timer circuit is disabled at the expiration of the first length of time. The override circuit disables the clamping circuit a second length of time after a power supply voltage exceeds a predetermined level.

REFERENCES:
patent: 5255146 (1993-10-01), Miller
patent: 5400202 (1995-03-01), Metz et al.
patent: 5463520 (1995-10-01), Nelson
patent: 5528188 (1996-06-01), Au et al.
Maloney & Dabri, Novel Clamp Circuits for IC Power Supply Protection, EOS/ESD Symposium, Paper 1.1, Phoenix, Ariz., Sep. 12, 1995.
Wheatley, Jr., On the Proportioning of Chip Area for Multistage Darlington Power Transistors, IEEE Trans. Electron. Devices, ED-23, pp. 870-878, 1976 .

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