Method and apparatus for providing electrostatic discharge prote

Electricity: electrical systems and devices – Safety and protection of systems and devices – Transient responsive

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361 56, 361 88, H02H 322

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active

058256032

ABSTRACT:
An arrangement for preventing damage to a circuit of an integrated circuit due to the occurrence of voltage transients introduced externally to the integrated circuit. According to one embodiment, the voltage transients are due to electrostatic discharge (ESD). The arrangement comprises a latch for coupling to an input pad of the integrated circuit. The latch asserts a first signal in response to sensing the occurrence of the voltage transient at the input pad. A transient protection circuit is coupled to the input pad for coupling the input pad to ground in response to the latch asserting the first signal such that current associated with the voltage transient is shunted to ground. A circuit is coupled to the latch for preventing the latch from asserting the first signal in response to the occurrence of the voltage transient if a predetermined condition exists. According to a present embodiment, the circuit is a timer that disables the latch in response to a supply output voltage VCC exceeding a predetermined level.

REFERENCES:
patent: 5255146 (1993-10-01), Miller
patent: 5400202 (1995-03-01), Metz et al.
patent: 5463520 (1995-10-01), Nelson
patent: 5528188 (1996-06-01), Au et al.
Maloney & Dabri, Novel Clamp Circuits for IC Power Supply Protection, EOS/ESD Symposium, Phoenix, Ariz., Sep. 12, 1995.
Wheatley, Jr., On the Proportioning of Chip Area for Multistage Darlington Power Transistors, IEEE Trans. Electron. Devices, ED-23, pp. 870-878, 1976 .

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