Electricity: electrical systems and devices – Safety and protection of systems and devices – Transient responsive
Reexamination Certificate
1999-06-16
2001-07-03
Sherry, Michael J. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Transient responsive
C361S056000, C361S091500
Reexamination Certificate
active
06256184
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits, and more particularly to a method and apparatus for providing electrostatic discharge protection for integrated circuits.
BACKGROUND OF THE INVENTION
Techniques for protecting integrated circuits from large, undesirable current and voltage signals due to electrostatic discharges, over-voltage conditions and the like (hereinafter “ESD events”) are well known. For example, each input/output (I/O) pad of an integrated circuit typically is provided with a diode coupled between the I/O pad and a reference terminal (e.g., ground) and a diode coupled between the I/O pad and a voltage terminal (e.g., V
dd
). In response to an ESD event that generates a large positive voltage on the I/O pad, the diode coupled between the I/O pad and the voltage terminal conducts and dissipates the large positive voltage from the I/O pad to the voltage terminal. However, the diode coupled between the reference terminal and the I/O pad is reverse biased and does not conduct in response to the positive voltage on the I/O pad (i.e., no direct path is generated between the I/O pad and the reference terminal).
Because no direct path exists between the I/O pad and the reference terminal for dissipating large positive voltages present on the I/O pad, the only path for dissipating such voltages from the I/O pad to the reference terminal is a path from the I/O pad to the voltage terminal (via the diode coupled therebetween), and from the voltage terminal to the reference terminal via the IC chip capacitance. The effectiveness/efficiency of this indirect voltage dissipation path depends sensitively on the IC chip's capacitance and the resistance of the voltage terminal bus. When either the IC chip's capacitance is small or the voltage terminal bus is highly resistive, poor ESD protection is afforded by the path from the I/O pad to the voltage terminal and from the voltage terminal to the reference terminal. Accordingly, a need exists for an improved method and apparatus for providing electrostatic discharge protection for integrated circuits, particularly for ESD events that generate large positive voltages on the I/O pads of IC chips.
SUMMARY OF THE INVENTION
To overcome the needs of the prior art, a novel ESD protection method and apparatus are provided for an IC chip having an I/O pad and I/O circuitry coupled to the I/O pad. Specifically, a low threshold voltage FET (e.g., a zero threshold voltage FET) is coupled to the I/O pad in parallel with the I/O circuitry for protecting the IC chip from an ESD event on the I/O pad. The FET also is coupled to a first voltage terminal (e.g., a reference terminal) of the I/O circuitry for providing a shunting path for the ESD event, thereby effectuating the protecting of the IC chip from the ESD event on the I/O pad. A first control circuit is coupled to a gate of the FET for maintaining the gate at a voltage level below a threshold voltage of the FET, thereby maintaining the FET in an off state during normal operation of the IC chip. Preferably a second control circuit is coupled between the FET and the first voltage terminal and operates in conjunction with the first control circuit for maintaining the FET in an off state during normal operation of the IC chip.
The first control circuit preferably comprises a short circuit between the gate of the FET and the first voltage terminal, an inverter coupled between the gate of the FET and a second voltage terminal (e.g., V
dd
) or a negative bias generator coupled to the gate of the FET. The second control circuit preferably comprises a short circuit between the FET and the first voltage terminal or a diode (e.g., an ESD rated diode) coupled between the FET and the first voltage terminal.
By employing the inventive method and apparatus for providing ESD protection, a direct path may be created between an I/O pad and a reference terminal for the dissipation of ESD events that generate positive voltages. IC chips having a small capacitance or a highly resistive voltage terminal bus thereby may be protected during ESD events. Further, because of the high substrate resistance associated with low or zero threshold voltage FETs, the ESD protection device turns on at lower trigger voltage levels than is possible with normal FETs.
Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description of the preferred embodiments, the appended claims and the accompanying drawings.
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Gauthier Jr. Robert J.
Nowak Edward J.
Voldman Steven H.
Williams Richard Q.
International Business Machines - Corporation
Schmeiser Olsen & Watts
Sherry Michael J.
Shkurko Eugene I.
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