Method and apparatus for providing deterministic read access to

Details Method and apparatus for providing deterministic read access to Method and apparatus for providing deterministic read access to

1996-01-12

1997-03-18

Harvey, Jack B.

395280, 395292, G06F 1300

Patent

active

056130759

ABSTRACT:
A method for guaranteeing access to a bus master for reads of main memory in a bridge circuit for joining a host processor, main memory, and a PCI bus, by detecting a read with data posted in the posted write buffer, disabling the posted write buffer, disabling access by the host processor for a selected period, detecting the presence of a retry of the read access, and enabling the posted write buffer after detecting an idle bus for the passage of the preselected time.

REFERENCES:
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patent: 4972313 (1990-11-01), Getson, Jr. et al.
patent: 5168568 (1992-12-01), Thayer et al.
patent: 5325499 (1994-06-01), Kummer et al.
patent: 5327570 (1994-07-01), Foster et al.
patent: 5379384 (1995-01-01), Solomon

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