Data processing: measuring – calibrating – or testing – Calibration or correction system – Circuit tuning
Reexamination Certificate
1999-06-22
2002-04-02
Shah, Kamini (Department: 2857)
Data processing: measuring, calibrating, or testing
Calibration or correction system
Circuit tuning
C326S027000, C326S030000, C326S083000, C326S087000
Reexamination Certificate
active
06366867
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present disclosure pertains to the field of testing integrated circuits. More particularly, the present disclosure pertains to testing the multiple separate subcomponents typically associated with compensated driver circuits.
2. Description of Related Art
Testing integrated circuits is a difficult yet important challenge. Improved testing techniques help ensure that high-quality and reliable parts are delivered to customers; however, as integrated circuits grow in size and complexity, the difficulty of thoroughly testing such components increases dramatically. The difficulty of testing integrated circuits further increases when the integrated circuits themselves compensate for varying operating conditions because different structures within the integrated circuit may be enabled to perform the same functions under different operating conditions.
One example of a circuit which may be compensated for varying operating conditions is an output buffer. Typically, a compensation circuit continuously or regularly monitors operating conditions and generates one or more compensation signals which are provided to the output buffer. The output buffer enables a number of subcomponents (e.g., parallel transistor legs) depending on the compensation signals provided by the compensation circuit. Accordingly, the current drive strength of the output buffer is adjusted according to the compensation signals. While the voltage waveform produced may be altered due to changing compensation signals, the actual output value does not change, making it difficult to detect the exact compensation factor value and/or the exact number of enabled parallel output stages at a given point in time.
One way to test integrated circuits with compensated output buffers is to functionally test the device under all expected operating conditions. If the output buffers provide the correct output within a design specification under all of the expected operating conditions, it may be assumed that the output buffer is functioning properly. This type of assumption, however, potentially masks structural defects in one or more subcomponents of the compensated output buffer. For example, it is possible that the buffer still meets its design specification but in fact has an inoperative subcomponent.
Unfortunately, even if the voltage waveforms of the actual signals produced by the buffer are analyzed, detection of the inoperative subcomponents of compensated buffers may remain difficult. In fact, several factors complicate the determination of whether a particular transistor leg causes a change in the output voltage waveform. First, the performance of other non-compensated circuits is affected by the change in operating conditions which caused the additional transistor leg to be enabled in the compensated buffer, thereby potentially obscuring the exact source of a changed voltage waveform. Additionally, changes in buffer switching noise or other complex power or circuit loading interactions may mask failures in the subcomponents of a compensated buffer.
Thus the failure of a subcomponent of a compensated driver circuit may escape detection in a variety of testing environments. Improperly functioning compensated driver circuits may decrease device or system reliability or may even cause failures under conditions that are not sufficiently stressed during testing. Additionally, undetected failures may lead to incorrect assumptions about the performance of such compensated circuits, and future designs based on these incorrect assumptions may be compromised.
Therefore, there is a continuing need to develop techniques to test the various structural components in a compensated circuit such as an output buffer or other driver circuit.
SUMMARY
A method and apparatus for providing controllable compensation factors to a compensated driver circuit which may be used to perform testing of the structural integrity of the compensated driver circuit is disclosed. One disclosed apparatus includes a compensated driver circuit having a number of subcomponents. At least one compensation factor, which may be provided by a compensation circuit, controls which of the subcomponents to enable. An additional circuit is coupled to provide controllable values for the at least one compensation factor.
BRIEF DESCRIPTION OF THE FIGURES
The present invention is illustrated by way of example and not limitation in the Figures of the accompanying drawings.
FIG. 1
illustrates one embodiment of a compensated buffer and associated circuitry for providing controllable compensation factors to the compensated buffer.
FIG. 2
illustrates details of one embodiment of a compensated buffer and some associated circuitry.
FIG. 3
is a flow diagram illustrating one embodiment of a method for testing compensated driver circuits.
REFERENCES:
patent: 5621739 (1997-04-01), Sine et al.
patent: 5869983 (1999-02-01), Ilkbahar et al.
patent: 5898321 (1999-04-01), Ilkbahar et al.
patent: 6031385 (2000-02-01), Ilkbahar
Ilkbahar Alper
Murray Scott W.
Sine Christopher John
Draeger Jeffrey S.
Intel Corporation
Shah Kamini
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