Method and apparatus for providing an optimized compare-and-bran

Details Method and apparatus for providing an optimized compare-and-bran Method and apparatus for providing an optimized compare-and-bran

1997-08-29

1999-02-09

Treat, William M.

395567, 395595, 395385, G06F 922

Patent

active

058705988

ABSTRACT:
An optimized compare-and-branch instruction for execution in a RISC type microprocessor. An instruction sequencer implemented in the microprocessor is responsive to a compare-and-branch instruction for efficient execution. The instruction sequencer detects a compare-and-branch instruction and executes it as a regular compare instruction. On the next cycle the instruction sequencer translates the instruction into a branch instruction and provides the translated instruction for execution by one of the execution units. The branch is executed, either taken or not taken, and normal program flow continues.

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