Method and apparatus for providing an optimized compare-and-bran

Details Method and apparatus for providing an optimized compare-and-bran Method and apparatus for providing an optimized compare-and-bran

1997-03-20

1998-05-05

Shah, Alpesh M.

39580041, G06F 900

Patent

active

057489505

ABSTRACT:
An optimized compare-and-branch instruction for execution in a RISC type microprocessor. An instruction sequencer implemented in the microprocessor is responsive to a compare-and-branch instruction for efficient execution. The instruction sequencer detects a compare-and-branch instruction and executes it as a regular compare instruction. On the next cycle the instruction sequencer translates the instruction into a branch instruction and provides the translated instruction for execution by one of the execution units. The branch is executed, either taken or not taken, and normal program flow continues.

REFERENCES:
patent: H1291 (1994-02-01), Hinton et al.
patent: 4783738 (1988-11-01), Li et al.
patent: 5333280 (1994-07-01), Ishikawa et al.
patent: 5448746 (1995-09-01), Eickemeyer et al.
patent: 5475853 (1995-12-01), Blaner et al.

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