Patent
1995-12-29
1998-10-13
Sheikh, Ayaz R.
395735, 395736, 395742, 395868, G06F 1324, G06F 1332
Patent
active
058225951
ABSTRACT:
An interrupt handler unit (IHU) for polling and arbitrating among interrupt sources and for generating a request for interrupt to a processor if winning priority is higher than an in-progress priority. The interrupt handler unit, upon acknowledgment by the processor, generates a vector address on an interface bus and at the same time pushes an acknowledged priority onto an in-progress priority (IPP) stack. The interrupt acknowledge is then provided to the appropriate interrupt source for the source to clear a pending flag. Upon a return from interrupt (RETI) instruction, the in-progress priority (IPP) stack is popped by the interrupt handler unit. The interrupt channels are time multiplexed based on interrupt state signals, and the individual interrupt sources can be masked. Interrupt related registers, (such as enable, priority, and flag) reside in the interrupt handler unit. The priority of an individual interrupt source is programmable using an interrupt priority registers, which are also provided in the IHU.
REFERENCES:
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patent: 5060139 (1991-10-01), Theus
patent: 5287523 (1994-02-01), Allison et al.
patent: 5469571 (1995-11-01), Bunnell
patent: 5530875 (1996-06-01), Wach
Etienne Ario
Intel Corporation
Sheikh Ayaz R.
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