Patent
1997-08-11
1999-07-06
Butler, Dennis M.
39518801, G06F 1300
Patent
active
059206900
ABSTRACT:
A method and apparatus for providing access protection in an integrated circuit (10). In one embodiment access protection circuitry (11) includes access attribute bits (51) which are compared to the access attributes (68) of a memory (14) request. If a mismatch occurs, an access fault signal (52) is asserted. If access fault signal (52) is asserted and a selective reset bit (48) has selected a first memory protection mode, then signal generation circuitry (44) asserts a reset signal (58). Reset signal (58) may be used to initiate a hardware reset of data processor (10). If access fault signal (52) is asserted and a selective reset bit (48) has selected a second memory protection mode, then signal generation circuitry (44) asserts an exception occurred signal (60).
REFERENCES:
patent: 5375243 (1994-12-01), Parzych et al.
patent: 5586301 (1996-12-01), Fisherman et al.
patent: 5809230 (1998-09-01), Pereira
Aslam Taimur
Moughanni Claude
Moyer William C.
Butler Dennis M.
Hill Susan C.
Hossain Abu
Motorola Inc.
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