Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1995-12-29
2002-09-17
Patel, Ajit (Department: 2662)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S469000, C370S395600, C370S466000
Reexamination Certificate
active
06452927
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bus communication architecture, more particularly, the present invention relates to serializing a parallel bus interface between an asynchronous transfer mode (ATM) layer and a physical (PHY) layer in an ATM system.
2. Art Background
ATM is a network protocol and switch-based method of communication which breaks down a communication process into several sub processes arranged in a stack. Each layer of the protocol stack provides services to the layer above it which allows the top most processes to communicate. Each layer communicates with another layer over defined interfaces enabling two different devices, using hardware and software from different manufacturers, but still conforming to the ATM model, to communicate over an ATM network. Using ATM, information sent over a network is segmented into a fixed length cell. The ATM cell has a fixed length of 53 bytes comprising 5 bytes of header information and 48 bytes of data information (e.g. voice, data, or video information).
Two layers in the protocol stack are the asynchronous transfer mode (ATM) layer and the physical (PHY) layer. The PHY layer interfaces directly to network media (e.g. fiber optics, twisted pair, etc.) and also handles transmission convergence (extracting ATM cells from the transport encoding scheme). The ATM layer and the PHY layer communicate over a parallel bus termed the Universal Test and Operations PHY Interface for ATM (UTOPIA) developed by the ATM forum. The UTOPIA bus is a bidirectional bus which transmits and receives ATM cells simultaneously. The UTOPIA bus is defined to support numerous transmission rates defined for ATM, including transmission rates as high as 622 Mbps. The UTOPIA bus defines two interface signal groups: Transmit and Receive. As illustrated in
FIG. 1
a
, the Transmit interface
16
moves data information from ATM layer
12
to PHY layer
14
, while the Receive interface
18
moves information from ATM layer
12
to PHY layer
14
.
As illustrated in
FIG. 1
b
, the Transmit interface comprises a parallel transmit data bus TxData
20
which may be, for example, 8-bits or 16-bits wide, and a number of control signals which may be utilized in the Octet Level Handshaking (OLH) mode or the Cell Level Handshaking (CLH) mode. In CLH mode data is moved between ATM layer
12
and PHY layer
14
as an entire uninterrupted cell. The transmit control signals include: transmit enable signal TxEnb*
22
which when asserted low by ATM layer
12
indicates that TxData
20
contains valid cell data; transmit start of cell signal TxSOC
24
which is asserted high by ATM layer
12
when TxData
20
contains the first valid byte of cell data; transmit full/cell available signal TxFull*/TxClav
26
which in CLH mode is asserted high by PHY layer
14
when it can accept a full cell of data, and is asserted low by PHY layer
14
when it is “full” and cannot accept a full cell of data; and transmit clock signal TxClk
28
which is provided by ATM layer
12
for synchronization of the data transfer from ATM layer
12
to PHY layer
14
.
Transmitting data from ATM layer
12
to PHY layer
14
in the CLH mode of operation is generally as follows. PHY layer
14
indicates to ATM layer
12
that it can accept a complete cell of data (53 bytes) by asserting TxFull*/TxClav to a high logic level. When ATM layer
12
has a complete cell to transfer to PHY layer
14
, it asserts TxEnb* to a low logic level and places the first byte of data onto data bus TxData
20
. Additionally, ATM layer
12
asserts TxSOC
24
to a high logic level along with the first byte of data. TxSOC
24
remains at a high logic level for the first cycle only. Each of the remaining
52
bytes of cell data are then transferred to PHY layer
14
at one byte per dock cycle of TxClk
28
.
In like manner,
FIG. 1
b
also illustrates the Receive interface comprising a parallel receive bus RxData
30
which may be, for example, 8-bits or 16 bits wide, and a number of control signals similar to the those described with respect to the Transmit interface. The receive control signals include: receive enable signal RxEnb*
32
which when asserted low by ATM layer
12
indicates that RxSOC
34
is valid and that RxData contains valid data; receive start of cell signal RxSOC
34
which is asserted by PHY layer
14
when RxData
30
contains the first valid byte of cell data; receive empty/cell available signal RxEmpty*/RxClav
36
which in CLH mode is asserted high by PHY layer
14
when it has a full cell of data to send to ATM layer
12
, and is asserted low by PHY layer
14
when it is “empty” and does not have a full cell of data to send to ATM layer
12
; and receive clock signal RxClk
38
which is provided by ATM layer
12
for synchronization of the data transfer from PHY layer
14
to ATM layer
12
.
Receiving data from PHY layer
14
at ATM layer
12
in the CLH mode of operation is generally as follows. PHY layer
14
indicates to ATM layer
12
that it has a complete cell of data (53 bytes) to send by asserting RxEmpty*/RxClav to a high logic level. When ATM layer
12
can receive a complete cell, it asserts RxEnb* to a low logic level. In the next clock cycle, PHY layer
14
places the first byte of data onto the data bus RxData
30
and asserts RxSOC
34
to a high logic level along with the first byte of data. RxSOC
34
remains at a high logic level for one cycle only. Each of the remaining 52 bytes of cell data are then transferred to ATM layer
12
at one byte per clock cycle of RxClk
38
.
Typical applications using UTOPIA include Network Interface Cards (NICs) and ATM switches. ATM switches typically are built using a rack mounted architecture which include individual shelves supporting PHY layer circuits or ATM layer circuits. Typically, the interconnect between the PHY layer circuits and the ATM layer circuits comprise wide parallel ribbon cables. The parallel ribbon cables may comprise as many as 40 conductors to accommodate the Transmit and Receive interfaces when the UTOPIA bus operates in a 16-bit mode. The use of wide ribbon cables to interconnect the ATM layer circuits and PHY layer circuits physically clutters the ATM switch. Additionally, the wide parallel ribbon cables connecting the various UTOPIA ports on a switch can extend to as much as a foot or more in length, depending on the distance between the PHY and ATM layer circuit shelves. The length of the ribbon cable poses a limitation on the ATM system as parallel ribbon cables, which operate reliably at one frequency over a given distance, may not operate reliably if that distance is increased.
UTOPIA ports generally operate at high frequencies (e.g. 25 MHz). Appreciably long ribbon cables operating at high speeds introduce undesirable problems such as cross-talk between conductors and voltage reflections due to the uncontrolled impedance of the ribbon cable. These problems cause degradation of signal integrity and skew problems in which the timing relationships of the signals transmitted between the ATM layer and the PHY layer are altered. Skew problems can result in the violation of set-up and hold timing parameters resulting in corruption of data.
One approach to address the signal integrity and skew problem is to employ specialized ribbon cable for transmitting differential signals, such as twisted pair conductors. However, this approach does not resolve the skew problem since skew can still result from differences in propagation delays for each signal through its respective differential driver, cable and receiver. Additionally, this approach doubles the number of conductors required for the parallel cable because each signal requires two conductors. Thus the already bulky ribbon cable further clutters the area between the ATM and PHY layer circuits.
Another approach is to use ribbon cables interconnected with repeater circuits. The repeater circuits would operate as a bridge to reliably increase the effective length of the ribbon cable. However, this approach also compounds
Cypress Semiconductor Corporation
Patel Ajit
Wagner , Murabito & Hao LLP
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