Method and apparatus for providing a high through put cache tag

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Details

395467, 395468, G06F 1314

Patent

active

054974704

ABSTRACT:
A cache tag controller for a cache tag memory for receiving multiple consecutive cache tag modify operations through a system bus to update cache tags in the cache tag memory. The cache tag controller comprises memory for storing cache tags; address register coupled to the memory for specifying a cache tag in the memory, the address register receiving a first modify operation from a system bus; read register coupled to the memory for reading the cache tag according to the address; first update circuit coupled to the read register for modifying the cache tag based on the first modify operation; stage register coupled to the first update circuit for storing an updated cache tag outputted from the first update circuit in response to the first modify operation; compare circuit coupled to the system bus for determining whether a second modify operation from the system bus is for the same cache tag in the memory as the first modify operation, the second modify operation being transmitted from said system bus before the first modify operation completes writing to the memory; second update circuit coupled to the stage register and compare circuit for modifying the updated cache tag in the stage register means according to the second modify operation if the modify operation is for the same cache tag as the first modify operation; and write register coupled to the memory for writing the first and second updated cache tags to the memory means as specified by the address from the address register.

REFERENCES:
patent: 5125083 (1992-06-01), Fite et al.
patent: 5224214 (1993-06-01), Rosich

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