Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2002-01-16
2004-09-14
Mancuso, Joseph (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S067000, C345S068000
Reexamination Certificate
active
06791516
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a gray level expression method for a plasma display panel, and more particularly to a method and apparatus for expressing a gray level with a decimal value in a plasma display panel that is capable of enhancing a picture quality.
2. Description of the Related Art
Generally a plasma display panel (PDP) radiates light from phosphors excited by an ultraviolet ray generated during a gas discharge, thereby displaying a picture including characters and graphics. Such a PDP is easy to be made into a thin-film and large-dimension type. Moreover, the PDP provides a very improved picture quality owing to a recent technical development.
Referring to
FIG. 1
, a conventional three-electrode, AC surface-discharge PDP, which is hereinafter referred to as “three-electrode PDP”, includes a scanning electrode Y and a sustaining electrode Z provided on an upper substrate
10
, and a data electrode X provided on a lower substrate
18
.
The scanning electrode Y and the sustaining electrode Z have transparent electrodes
12
Y and
12
Z with a large width and metal bus electrodes
13
Y and
13
Z with a small width, respectively, and are formed on the upper substrate in parallel. An upper dielectric layer
14
and a protective film
16
are disposed on the upper substrate
10
in such a manner to cover the scanning electrode Y and the sustaining electrode Z. Wall charges generated upon plasma discharge are accumulated in the upper dielectric layer
14
. The protective film
16
prevents a damage of the upper dielectric layer
14
caused by a sputtering during the plasma discharge and improves the emission efficiency of secondary electrons. This protective film
16
is usually made from magnesium oxide (MgO). The data electrode X is crossed to the scanning electrode Y and the sustaining electrode Z.
A lower dielectric layer
22
and barrier ribs
24
are formed on the lower substrate
19
. The surfaces of the lower dielectric layer
22
and the barrier ribs
24
are coated with a fluorescent material layer
26
. The barrier ribs
24
separate discharge spaces being adjacent to each other in the horizontal direction to thereby prevent optical and electrical crosstalk between adjacent discharge cells. The fluorescent layer
26
is excited by an ultraviolet ray generated during the plasma discharge to generate any one of red, green and blue visible light rays. An inactive mixture gas of He+Xe, Ne+Xe or He+Xe+Ne is injected into a discharge space defined between the upper and lower substrate
10
and
18
and the barrier rib
24
.
In a PDP, one frame is divided into a plurality of sub-fields which are different from each other in the number of discharge, so as to realize gray levels of a picture. Each sub-field is again divided into a reset period for uniformly causing a discharge, an address period for selecting the discharge cell and a sustaining period for realizing the gray levels depending on the discharge frequency.
For instance, when it is intended to display a picture of 256 gray levels, a frame equal to {fraction (1/60)} second (i.e. 16.67 msec) is divided into 8 sub-fields SF
1
to SF
8
as shown in FIG.
2
. Each of the 8 sub-fields SF
1
to SF
8
is again divided into a reset period, an address period and a sustaining period. The reset period and the address period of each sub-field are equal every sub-field. The address discharge for selecting the cell is caused by a voltage difference between the data electrode X and the scanning electrode Y. The sustaining period is increased at a ration of 2
n
(wherein n=0, 1, 2, 3, 4, 5, 6 and 7) at each sub-field. A sustaining discharge frequency in the sustaining period is controlled at each sub-field in this manner, to thereby realize gray levels.
FIG. 3
illustrates driving waveforms applied to the scanning electrode Y, the sustaining electrode Z and the data electrode X at the first to third sub-fields having a low brightness weighting value.
Referring to
FIG. 3
, a reset period for initializing a panel is assigned at an initial time of the frame. In the reset period, a high positive reset pulse RST is applied to the sustaining electrode Z to cause a reset discharge within cells of the panel. Since this reset discharge allows wall charges to be uniformly accumulated in the cells of the panel, a discharge characteristic becomes uniform.
Each of the first to third sub-fields SF
1
to SF
3
includes an address period, a sustaining period and an erase period. Herein, the address periods and the erase periods are set equally, whereas the sustaining periods become different depending upon a brightness weighting value given to each sub-field SF
1
to SF
3
.
The first sub-field SF
1
has a brightness weighting value set to 2
0
. In the address period of the first sub-field SF
1
, a data pulse DATA is applied to the address electrode X and a scanning pulse-SCN is sequentially applied to the scanning electrode Y in such a manner to be synchronized with the data pulse DATA. A voltage difference between the data pulse DATA and the scanning pulse-SCN is added to a wall voltage within the cells, thereby allowing the cells supplied with the data pulse DATA to cause an address discharge. In the sustaining period of the first sub-field SF
1
, a sustaining pulse is once applied to each of the scanning electrode Y and the sustaining electrode Z in correspondence with the brightness weighting value ‘2
0
’. The cells selected in the address period are discharged for each sustaining pulse while the sustaining pulse being added to an internal wall voltage to thereby have total twice discharge. In the erase period of the first sub-field SF
1
, an erase signal ERASE with a shape of ramp wave is applied to all the scanning electrodes Y. This erase signal ERASE erases a sustaining discharge and uniformly forms a certain amount of wall charges within the cells of the panel.
The second sub-field SF
2
has a brightness weighting value set to 2
1
while the third sub-field SF
3
has a brightness weighting value set to 2
2
. The address periods of the second and third sub-fields SF
2
and SF
3
cause an address discharge within the cells supplied with the data pulse DATA in similarity to that of the first sub-field SF
1
to select the cell. In the sustaining period of the second sub-field SF
2
, a sustaining pulse is twice applied to each of the scanning electrode Y and the sustaining electrode Z in correspondence with the brightness weighting value ‘2
1
’. In the sustaining period of the third sub-field SF
3
, a sustaining pulse is four times applied to each of the scanning electrode Y and the sustaining electrode Z in correspondence with the brightness weighting value ‘2
2
’. Accordingly, total four times discharge are generated at each of the cells selected by an address discharge in the sustaining period of the second sub-field SF
2
, whereas total eight times discharge are generated at each of the cells selected by an address discharge in the sustaining period of the third sub-field SF
3
.
The conventional PDP driving method has a problem in that it is unable to express a gray level less than 1. More specifically, the conventional PDP expresses a gray level with an integer value by a combination of sub-fields, to each of which a brightness weighting value of an integer is set, as seen from the following Table 1. A brightness weighting value of each sub-field becomes equal to the number of sustaining pulse pairs.
The following Table represents on/off of the sub-field according to a gray level value in the case of 8-bit default code.
TABLE 1
SF1 (1)
SF2 (2)
SF3 (4)
SF4 (8)
SF5 (16)
SF6 (32)
SF7 (64)
SF8 (128)
0
x
x
x
x
x
x
x
x
1
0
x
x
x
x
x
x
x
2
x
0
x
x
x
x
x
x
3
0
0
x
x
x
x
x
x
4
x
x
0
x
x
x
x
x
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
126
x
0
0
0
0
0
0
x
127
0
0
0
0
0
0
0
x
128
x
x
x
x
x
x
x
0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
252
x
x
0
0
0
0
0
0
253
0
x
0
0
0
0
0
0
254
x
0
0
0
0
0
0
0
255
0
0
0
0
0
0
0
0
In the Table 1, the uppermost
Fleshner & Kim LLP
LeFlore Laurel E.
LG Electronics Inc.
Mancuso Joseph
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