Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1998-06-03
2001-07-24
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S013000, C703S015000
Reexamination Certificate
active
06266630
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to simulation of circuit designs; and more specifically, the present invention relates to a graphical representation of simulation of designs having analog and mixed signals.
BACKGROUND OF THE INVENTION
As the scale of complexity provided by integrated circuits (ICs) and related systems increases, the number of functional units included on a single die may be increased because each circuit consumes comparatively less space than before. One result of this trend is that ICs, such as processors, that have traditionally been completely digital are increasingly including analog components, such as analog-to-digital (A/D) converters, digital-to-analog (D/A) converters and phased locked loop (PLL) circuits. These ICs having both analog and digital components are known as mixed signal, or analog mixed-signal (AMS) ICs.
Because processors and other complex circuits are expensive to fabricate, designs are typically thoroughly simulated with software simulation languages such as HDL (Hardware Description Language) and VHDL (VHSIC Hardware Description Language, where VHSIC denotes “Very High Speed Integrated Circuit”). VHDL is described in greater detail in “IEEE Standard VHDL Language Reference Manual,” ANSI Std. 1076-1993, Published Jun. 6, 1994. These simulation programs provide simulation and debugging for digital components. However, they do not provide simulation of analog or mixed-signal components. For this reason, designers were required to simulate analog components with simulation software such as SPICE that provide analog circuit simulation. Analog simulation, however, typically requires a much lower level of programming than digital simulation.
In order to expedite simulation of mixed-signal designs, mixed-signal extensions to HDL (HDL-A™), VHDL (VHDL-AMS), and Verilog-A (Verilog-AMS) have been designed. VHDL-AMS is described in greater detail in 1076.1 Language Design Committee, several papers under the generic name “White Papers”, IEEE 1076.1 Internal work, 1996 and “1076.1 Working Document: Definition of Analog Extensions to IEEE Standard VHDL”, IEEE 1076.1 Committee Internal work, Jul., 1997. These extensions provide circuit designers with a single software tool to simulate mixed signal designs. Because these unified simulation programs are extensions to previous digital simulation programs, the digital portion of the programs are largely unchanged.
The analog simulation provided by mixed-signal simulation programs typically model the analog systems using differential and algebraic equations (DAEs), including Kirchoffs Current Law (KCL) and Kirchoffs Voltage Law (KVL), which describe the interconnection of circuit elements. Because the mathematical model of analog circuits include a large number of non-linear differential equations, simulations are time consuming, even with high-speed computer systems. Simplifications, such as One Step Relaxation (OSR), Newton-Raphson Method (NRM) and Integral Equation Method (IEM) have been used. However, each requires solving sets of equations until convergence.
During simulation, the designer must wait until convergence or until a predetermined time period has elapsed to determine whether the DAEs describing the circuit converge. A need exists therefore, to provide the designer with graphical feedback during the solution of the DAEs or other equations so that he or she may monitor whether convergence occurs and at what rate convergence occurs.
SUMMARY OF THE INVENTION
A method and apparatus for providing a graphical user interface for simulating designs with mixed signals is described. A graphical representation of one or more test values corresponding to simulated conditions is generated. The test values are determined by an iterative simulation process. An indication is provided by the graphical representation for each iteration of the iterative simulation process. The graphical representation is displayed by a display device.
REFERENCES:
patent: 4868770 (1989-09-01), Smith et al.
patent: 4985860 (1991-01-01), Vlach
patent: 5297066 (1994-03-01), Mayes
patent: 5920484 (1999-07-01), Nguyen et al.
patent: 5963724 (1999-10-01), Mantooth et al.
Smith et al., “Mixed-Signal Circuit Simulation System with Behavioral Modeling Capability”, Conference Record Southcon/94, pp. 580-583, Mar. 1994.*
Ho et al., “Wavelet Representation for Multigrid Computation in Surface Interpolation Problem”, Proceedings of the 13th International Conference on Pattern Recognition, 1996, pp. 740-744, vol. 1, Aug. 1996.*
Uresin et al., “Effects of Asynchronism on the Convergent Rate of Iterative Algorithms”, Journal of Parallel and Distributed Computing, vol. 34, Issue 1, pp. 66-81, Apr. 10, 1996.*
Lee et al., “Digital Filter Design Using Genetic Algorithm”, IEEE Symposium on Advances in Digital Filtering and Signal Processing, 1998, pp. 34-38, Jun. 1998.*
Bertsekas et al., “Convergence Rate and Termination of Asynchoronous Iterative Algorithms”, Proceedings of the Third International Conference on Supercomputing, pp. 461-470, Jun. 1989.*
Wang et al., “Design and Test of Mixed-Signal VLSI”, Canadian Conference on Electrical and Computer Engineering, pp. 461-464, vol. 1, Sep. 1993.*
Gielen et al., “Analog Behavioral Models for Simulation and Sysnthesis of Mixed-Signal Systems”, Proceedings of the Third European Conference on Design Automation, pp. 464-468, Mar. 1992.*
Yost et al., “Content-Based Visualization for Intelligent Problem-Solving Environments”, Internations Journal of Human-Computer Studies, vol. 46, Issue4, pp. 409-441, Apr. 1997.
Cirigliano Jean-Pierre
Garcia-Sabiro Serge F.
Hui-Bon-Hoa Christophe P.
Kission Polen
Raynaud Philippe P.
Blakely , Sokoloff, Taylor & Zafman LLP
Mentor Graphics Corporation
Sergent Douglas W.
Teska Kevin J.
LandOfFree
Method and apparatus for providing a graphical user... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for providing a graphical user..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for providing a graphical user... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2511272