Method and apparatus for providing a dual-loop phase lock loop

Details Method and apparatus for providing a dual-loop phase lock loop Method and apparatus for providing a dual-loop phase lock loop

2011-08-23

2011-08-23

Trinh, Sonny (Department: 2618)

Telecommunications

Receiver or analog modulated signal frequency converter

Signal selection based on frequency

C455S260000, C455S264000

Reexamination Certificate

active

08005447

ABSTRACT:
A method and apparatus for providing a dual-loop phase lock loop (PLL) for a radio-frequency (RF) receiver is provided. The dual-loop PLL may include coarse tuning circuitry and fine tuning circuitry. The coarse turning circuitry and fine tuning circuitry may be arranged in parallel. Both of the coarse tuning circuitry and fine tuning circuitry provide respective tuning signals to a voltage-controlled oscillator (e.g., a varactor tuned VCO). The coarse tuning circuitry and the fine tuning circuitry may provide the respective tuning signals simultaneously. In addition, coarse and fine tuning circuitry may be formed monolithically with other elements of the dual-loop PLL so as to provide a highly-integratable having a wide frequency lock range and high sensitivity.

REFERENCES:
patent: 6215835 (2001-04-01), Kyles
patent: 6570948 (2003-05-01), Marshall
patent: 6856182 (2005-02-01), Moyal
patent: 6931243 (2005-08-01), Goldman
patent: 7177611 (2007-02-01), Goldman
patent: 2007/0176694 (2007-08-01), Rhee et al.
patent: 2008/0088379 (2008-04-01), Chen
patent: 2008/0252383 (2008-10-01), Lee et al.

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