Method and apparatus for protection from over-erasing...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185240, C365S185300

Reexamination Certificate

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11223552

ABSTRACT:
Charge trapping memory cells are protected from over-erasing in response to an erase command. For example, in response to an erase command, one bias arrangement is applied to program charge trapping memory cells, and another bias arrangement is applied to erase the charge trapping memory cells, such that the charge trapping memory cells have a higher net electron charge in the erased state than in the programmed state. In another example, an integrated circuit with an array of charge trapping memory cells has logic which responds to an erase command by applying similar bias arrangements to the charge trapping memory cells. In a further example, such an integrated circuit is manufactured.

REFERENCES:
patent: 5963476 (1999-10-01), Hung et al.
patent: 6188604 (2001-02-01), Liu et al.
patent: 6834012 (2004-12-01), He et al.
patent: 7075828 (2006-07-01), Lue et al.
patent: 7133313 (2006-11-01), Shih
patent: 2002/0159297 (2002-10-01), Yoshida
patent: 2005/0052228 (2005-03-01), Yeh et al.
patent: 2005/0237815 (2005-10-01), Lue et al.
C.C Yeh et al. “PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per cell Flash Memory” IEEE 2002, pp. 931-934.

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