Method and apparatus for protecting content of semiconductor non

Details Method and apparatus for protecting content of semiconductor non Method and apparatus for protecting content of semiconductor non

1997-10-03

1999-04-20

Yoo, Do-Hyun

Static information storage and retrieval

Floating gate

Particular biasing

36518511, 36518909, 365222, 36523003, G11C 700

Patent

active

058963189

ABSTRACT:
Described are method and apparatus for protecting content of a semiconductor non-volatile memory and a semiconductor non-volatile memory itself, the semiconductor non-volatile memory being constituted by, for example, a flash memory, so that a reduction in a life time of the non-volatile memory due to an excess number of times a refresh (rewrite) operation can be prevented. For example, a first data deterioration determining voltage V.sub.1 is applied via a row decoder to one of word lines to which a selected bit is connected to determine whether the selected bit is turned on and a second data deterioration determining voltage V.sub.2 is applied to the same word line to determine whether the selected bit is turned off. The results of the determinations are stored in a second memory unit. If the selected bit is turned on in the former result and is turned off in the latter result, a control circuit determines that the data in the selected bit is deteriorated and carries out the refresh operation for the selected bit. The value of V.sub.1 is set which falls in a voltage range from a relatively high threshold voltage to a rated power supply voltage (V.sub.CC) and the value of V.sub.2 is set which falls in a voltage range from the power supply voltage (V.sub.CC) to a relatively low threshold voltage.

REFERENCES:
patent: 5390148 (1995-02-01), Saito
patent: 5444664 (1995-08-01), Kuroda et al.
patent: 5467357 (1995-11-01), Asami
patent: 5825690 (1998-10-01), Saitoh
VLSI Design Techniques For Analog and Digital Circuits (pp. 824 to 831) Thereof are Attached Herein (Copyright at 1990).
IEEE J Paper Tilted An 80-NS 1MB Flash Memory With On-Chip Erase/Erase-Verify Controller Found in pp. 327 to 330 Preprinted For IEEE J. Solid-State Circuits, vol. 25, No. 5, pp. 1147-1152, Oct. 1990.

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