Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – Plural non-isolated transistor structures in same structure
Reexamination Certificate
1999-07-21
2001-05-01
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
Plural non-isolated transistor structures in same structure
C257S554000, C257S556000, C257S557000, C257S560000, C257S561000, C257S563000, C257S576000, C257S577000
Reexamination Certificate
active
06225679
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method and apparatus for protecting a circuit connection pad against electrostatic voltage surges.
2. Discussion of the Related Art
The problem of protecting an integrated circuit against surge voltages and electrostatic discharges is well known. It is desirable to prevent destruction or deterioration of elements of internal circuitry of the integrated circuit. For this purpose, protection devices are used to dissipate the energy. These devices are designed to become activated from a certain voltage level upwards and are capable of conducting high current.
A well-known protection device comprises a series protection resistor Rp coupled between a connection pad PS, an input or output pad, of the integrated circuit and an input or output terminal B
1
of internal circuitry to be protected. A lateral bipolar transistor Tb is connected between this connection pad PS and ground, a base of which is also connected to ground as shown in FIG.
1
.
A standard structure of an NPN bipolar transistor on a P-type substrate comprises two N type diffusions, one corresponding to the emitter and the other to the collector. The base corresponds to a substrate zone between the emitter and the collector. The substrate is biased to ground by a resistive P+ substrate connector. The two diffusions are insulated by a field oxide layer beneath which, conventionally, there is the field, implantation, referenced Piso, i.e., a P-type zone with higher doping than the substrate. The breakdown voltage of a device of this kind depends on the doping of the N type diffusion and the doping of the field implantation Piso. In known CMOS technologies, which include making an implantation of the same type as the substrate made on the entire substrate except in regions of opposite type tubs (these are the technologies known as twin-tub technologies) to prevent the tubs from widening excessively, there will then be a breakdown voltage on the order of 12 to 15 volts.
As soon as the voltage at the connection pad PS reaches or goes beyond this level, the well-known process of protection will be activated, as shown in
FIGS. 2
a
and
2
b
, with a conduction by collector-base breakdown or disruption followed by a passage of the collector-emitter into forward bias. The following occurs:
(1) The collector-base junction (if it is the collector that is connected to the pad) breaks down, causing a current ib to flow in the base.
(2) Since the base is resistive, the base-emitter voltage Vbe increases with the current ib until it reaches 0.6 volts.
(3) The base-emitter voltage Vbe, upon reaching 0.6 volts, forward biases the base-emitter junction, which then lets through a high current (bipolar conduction).
The protection resistor Rp, for its part, enables the limiting of the current in the logic circuitry that is to be protected.
There is also a known improved lateral bipolar transistor structure that can be used to protect the circuit for far higher breakdown voltage levels, e.g., in the range of 40 to 100 volts. This is obtained by placing the N type diffusion of the collector, if it is the collector that is connected to the pad to be protected, entirely in an N type tub. It should be noted that a tub corresponds to an implantation of impurities at a greater depth but with a lower concentration than the diffusion which is a surface diffusion. In one example, the N type tub has a depth of 2.2 microns with a doping of 8×10
12
atoms/cm
3
, and the diffusion has a thickness of 0.15 microns with a doping of 5×10
15
atoms/cm
3
. A junction between the N type tub and the P-type substrate therefore has a breakdown voltage that is far higher than the junction between the N type diffusion and the P-type substrate, since the tub is far less doped.
In certain integrated circuits, however, connection pads are designed for transmission at input or at output of high voltage levels, for example, in the range of 20 volts. If it is sought to protect these connection pads, it is necessary first of all to enable the transmission of the desired level of high voltage without activating the protection. It can be seen that it is not possible to use the standard lateral bipolar transistor structure since a breakdown voltage of 12 to 15 volts is obviously far too low. However, the modified structure of the bipolar transistor, wherein the diffusion is placed entirely in a tub to increase the breakdown voltage, is not appropriate for all applications either. Indeed, it has been seen that this structure provides a very high breakdown voltage, e.g., in the range of 40 to 100 volts. Certain applications require tight protection of the level of the high voltage transmitted to the pad, namely protection at a level that is just slightly higher than the transmitted voltage. For example, if the maximum level of the highest voltage transmitted to the pad is equal to 19 volts, it is sought to be able to activate the protection device at 20 volts at least.
Furthermore, a metal connection of the collector to the pad and the resistor must provide efficient protection. Indeed, the physical position at which the metal contact is made should not be capable of disrupting any junction other than the collector-base junction at which this disruption is desired.
None of the known structures of the related art can be used to resolve this problem.
This technical problem arises especially in integrated circuits including an EEPROM memory that uses an internally generated programming/erasure voltage on the order of 19 volts (with integrated load pump and multipliers) as shown schematically in FIG.
1
. To enable the testing and characterizing of these memory circuits, there is provided a connection pad PS on which the high voltage level Vpp can be switched over to the output pad through a high voltage switch-over transistor (T
1
, COM).
SUMMARY OF THE INVENTION
The present invention proposes to resolve the technical problem referred to here above.
In the invention, a method is sought that makes it possible to have a protection device adapted to protect a high voltage transmission pad.
As characterized, the invention therefore relates to a method for the manufacture, in CMOS technology on a P-type substrate, of a structure for the protection of a connection pad against surge voltages or electrostatic discharges. The structure comprises a protection series resistor between the internal circuitry to be protected and said connection pad and a lateral bipolar transistor with a first N type diffusion and a second N type diffusion to form an emitter and a collector, the intermediate region forming the base of said transistor, and one of the diffusions being connected to said pad to be protected. According to the invention, this diffusion connected to the pad is made in an N type tub with a zone that extends laterally outside the tub in the base, a P-type implantation being made on the entire substrate outside the N type tub except in the region of the base of said lateral transistor in which said zone extends.
One embodiment is directed to a protection device to protect an integrated circuit in CMOS technology on a P-type substrate including a series protection resistor disposed between internal circuitry to be protected and a connection pad, a lateral bipolar transistor including a first N type diffusion to form an emitter of the lateral bipolar transistor, a second N type diffusion to form a collector of the lateral bipolar transistor and an intermediate region forming a base of said transistor. One of the N-type diffusions is connected to said connection pad and the N-type diffusion that is connected to the connection pad is made in an N-type tub with a zone that extends laterally outside the tub in the base. A P-type implantation is made on the entire substrate outside the N-type tub and not in the region of the base of said lateral transistor in which said zone does not extend.
Another embodiment is directed to a method of providing a circuit to protect against voltage surges in a
Fournel Richard
Marinet Fabrice
Fenty Jesse A
Galanthay Theodore E.
Lee Eddie C.
Morris James H.
SGS-Thomson Microelectronics S.A.
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