Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-01-26
2001-08-14
Karlsen, Ernest (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06275058
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to a test method and apparatus for burn-in testing of integrated circuits in a parallel test environment.
2. Description of the Related Art
It is well known in the field of integrated circuits (IC) devices that proper testing during and after fabrication is important to improving the reliability and yield of product shipped to the customers. During manufacture by the chip maker, ICs typically undergo three separate test cycles: (1) in-process testing, such as continuous monitoring of sheet resistivities, junction depths, and other pertinent device parameters, such as current gain and voltage breakdown; (2) preliminary electrical testing called the wafer-probe test which is performed prior to the scribing and the separation steps; and (3) a detailed final testing of reliability and performance after the completion of the fabrication and packaging steps.
The testing of ICs is one of the most expensive and time consuming stages of the manufacturing process. It is desirable to keep testing costs low, since these add directly to the cost of producing the parts. However, the cost of testing cannot be lowered too far, as doing so comes at the expense of product reliability.
Automatic high-speed testing is practically mandatory to the final testing of modern ICs because a larger number of complex tests are required to check even the simplest types of circuits. The testing is typically performed by a memory controller or processor (or a designated processor in a multi-processor machine) which runs a testing program.
Random access memory (RAM) integrated circuits, such as DRAMs and the like, include an array of memory cells arranged in rows and columns. Detailed final testing of reliability and performance after the completion of the fabrication and packaging steps is typically performed to determine whether there is an actual or latent defect in one or more of the memory cells which would render a memory unreliable. For example, to determine if a hidden defect exists, random access memories are typically subjected to data retention tests and/or data march tests. In data retention tests, every cell of the memory is written and checked after a prespecified interval to determine if leakage current has occurred that has affected the stored logic state. In a march test, a sequence of read and/or write operations is applied to each cell, either in increasing or decreasing address order. To determine if there is a defect in the array of bits that may fail over time, burn-in testing is typically performed to accelerate failure using voltage and temperature stress. When a failed memory cell is detected through testing, the column or row in which the failed memory cell is located is typically substituted by a redundant column or row of memory cells.
In order to reduce the time required to perform the testing of memory chips, the testing process is performed on a plurality of memory devices simultaneously.
FIG. 1
illustrates in block diagram form a conventional testing system
20
used to perform tests on integrated circuits such as memory devices. Test system
20
may include a controller
22
which controls a test device
24
. Controller
22
may include a microprocessor, such as a general purpose single- or multi-chip microprocessor. In addition, the microprocessor may be any conventional special purpose microprocessor such as a digital signal processor or a graphic processor. Signals between the controller
22
and test device
24
are sent via communication path
23
. Test device
24
is connected, via communication path
25
, to a device under test (DUT) board
26
. DUT
26
contains the memory devices being tested, and can be placed separate from test device
24
in order to perform environmental testing if desired. For example, burn-in testing is typically performed at an elevated ambient temperature in a thermal chamber. Power supply
30
supplies power (Vcc) to DUT
26
for operation via conductor
32
.
FIG. 2
illustrates in block diagram form the DUT
26
of FIG.
1
. DUT
26
includes a plurality of sockets
40
into which the items being tested, such as memory chips, are inserted. Each socket
40
is connected to a power source Vcc from power supply
30
via conductor
42
. A fuse
44
or other protective device is provided between each socket
40
and Vcc conductor
42
. Each socket
40
receives signals from and sends signals to test device
24
via bus line
46
,
48
and
50
. These signals may include input/output (I/O) signals, address signals, and so forth as are necessary for a memory chip inserted in socket
40
to be properly tested.
The operation of test system
20
is as follows. A memory chip may be inserted into each socket
40
. Each memory chip is powered by a supply voltage Vcc through fuse
44
from power supply
30
. Controller
22
executes a program to control test device
24
to run through a test sequence. Test device
24
, in response to the signals from controller
22
, performs various tests on each memory device on DUT
26
, such as data retention, data march, and burn-in tests previously described. Based on the results of the tests performed, test device
24
determines if a memory device on DUT
26
is faulty. Each fuse
44
provides protection for its respective socket
40
and also DUT
26
in the case where a fault in the memory chip causes an over-current condition. If the fuse
44
opens due to some high current fault condition, power to the respective socket
40
is interrupted and the device inserted into socket
40
will not operate, despite the signals being sent to it from test device
24
via bus lines
50
,
48
and
46
.
There are problems, however, with the conventional test system as described with respect to
FIGS. 1 and 2
. Certain types of memory chips, such as for example a Synchronous DRAM (SDRAM) and the like, may still partially operate even if the fuse
44
of the socket
40
into which the chip is inserted has operated and is blown. For example, the signals from test device
24
on the address and I/O lines via bus lines
50
,
48
and
46
may provide sufficient power to a SDRAM to keep the chip partially active even if the power source Vcc is interrupted by the opening of fuse
44
. In this partially active state, the chip may not operate normally and may cause erroneous signals on the shared bus lines
48
,
50
. Specifically, the chips may still maintain the ability to generate data at random times, such as for example a strong logic zero, and output it to test device
24
. Test device
24
may interpret this randomly generated data signal indicating a failed test on one of the otherwise good chips on DUT
26
, or alternatively may interpret the randomly generated data signal as indicating a passed test on one of the other wise faulty chips. These erroneous interpretations may lead to faulty chips not being repaired or good chips being rejected, and may significantly decrease the efficiency of the test system and corresponding reliability of the memory devices being sent to customers.
Thus, there exists a need for an apparatus and method for testing IC devices which can reliably prevent chips that should not be active due to a blown fuse from generating random data signals which can adversely impact the test results of other chips being tested.
SUMMARY OF THE INVENTION
In accordance with the present invention, a test system and method are described and illustrated which do not exhibit the drawbacks associated with the previous test systems. According to the present invention, the state of the fuse that protects each socket is determined by a controller, such as an Application Specific Integrated Circuit (ASIC), built onto the test board. When it is determined that a specific fuse is open, i.e., the fuse has blown due to some high current fault condition, the part inserted into the socket protected by the fuse will have its I/O lines disabled by the controller, thereby effectively shutti
Lunde Aron T.
Rasmussen Phillip A.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Karlsen Ernest
Micro)n Technology, Inc.
Tang Minh
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