Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-11-07
2006-11-07
Auduong, Gene N. (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180
Reexamination Certificate
active
07133317
ABSTRACT:
Programming nonvolatile memory cells is affected by the program disturb effect which causes data accuracy issues with nonvolatile memory. Rather than masking the voltage conditions that cause the program disturb effect, voltages are applied to neighboring nonvolatile memory cells, which takes advantage of the program disturb effect to program multiple cells quickly.
REFERENCES:
patent: 4959812 (1990-09-01), Momodomi et al.
patent: 5270969 (1993-12-01), Iwahashi
patent: 5278439 (1994-01-01), Ma et al.
patent: 5355464 (1994-10-01), Fandrich et al.
patent: 5408115 (1995-04-01), Chang
patent: 5424569 (1995-06-01), Prall
patent: 5448517 (1995-09-01), Iwahashi
patent: 5483486 (1996-01-01), Javanifard et al.
patent: 5485422 (1996-01-01), Bauer et al.
patent: 5509134 (1996-04-01), Fandrich et al.
patent: 5515324 (1996-05-01), Tanaka
patent: 5566120 (1996-10-01), D'Souza
patent: 5602775 (1997-02-01), Vo
patent: 5644533 (1997-07-01), Lancaster et al.
patent: 5694356 (1997-12-01), Wong et al.
patent: 5745410 (1998-04-01), Yiu et al.
patent: 5768192 (1998-06-01), Eitan
patent: RE35838 (1998-07-01), Momodomi et al.
patent: 5895949 (1999-04-01), Endoh et al.
patent: 5966603 (1999-10-01), Eitan
patent: 6011725 (2000-01-01), Eitan
patent: 6034896 (2000-03-01), Ranaweera et al.
patent: 6074917 (2000-06-01), Chang et al.
patent: 6096603 (2000-08-01), Chang et al.
patent: 6172907 (2001-01-01), Jenne
patent: 6194272 (2001-02-01), Sung
patent: 6215148 (2001-04-01), Eitan
patent: 6219276 (2001-04-01), Parker
patent: 6297096 (2001-10-01), Boaz
patent: 6320786 (2001-11-01), Chang et al.
patent: 6363013 (2002-03-01), Lu et al.
patent: 6396741 (2002-05-01), Bloom et al.
patent: 6436768 (2002-08-01), Yang et al.
patent: 6458642 (2002-10-01), Yeh et al.
patent: 6487114 (2002-11-01), Jong et al.
patent: 6512696 (2003-01-01), Fan et al.
patent: 6538923 (2003-03-01), Parker
patent: 6552386 (2003-04-01), Wu
patent: 6566699 (2003-05-01), Eitan
patent: 6587903 (2003-07-01), Roohparvar
patent: 6614070 (2003-09-01), Hirose et al.
patent: 6614694 (2003-09-01), Yeh et al.
patent: 6643181 (2003-11-01), Sofer et al.
patent: 6643185 (2003-11-01), Wang et al.
patent: 6646924 (2003-11-01), Tsai et al.
patent: 6657894 (2003-12-01), Yeh et al.
patent: 6670240 (2003-12-01), Ogura et al.
patent: 6670671 (2003-12-01), Sasago et al.
patent: 6690601 (2004-02-01), Yeh et al.
patent: 6714457 (2004-03-01), Hsu et al.
patent: 6795342 (2004-09-01), He et al.
patent: 6912163 (2005-06-01), Zheng et al.
patent: 6937511 (2005-08-01), Hsu et al.
patent: 2002/0167844 (2002-11-01), Han et al.
patent: 2002/0179958 (2002-12-01), Kim
patent: 2003/0036250 (2003-02-01), Lin et al.
patent: 2003/0185055 (2003-10-01), Yeh et al.
patent: 2004/0084714 (2004-05-01), Ishii et al.
patent: 2004/0145024 (2004-07-01), Chen et al.
patent: 2005/0001258 (2005-01-01), Forbes
patent: 09162313 (1997-06-01), None
patent: 11233653 (1999-08-01), None
patent: WO 94/28551 (1994-12-01), None
U.S. Appl. No. 11/085,444, filed Mar. 21, 2005, entitled “Method for Manufacturing a Multiple-Gate Charge Trapping Non-Volatile Memory,” 71 pages.
U.S. Appl. No. 10/855,286, filed May 26, 2004, entitled “Nand-Type Non-Volatile Memory Cell and Method for Operating Same,” 15 pages.
U.S. Appl. No. 11/085,458, filed Mar. 21, 2005, entitled “Charge Trapping Non-Volatile Memory and Method for Gate-by-Gate Erase for Same,” 73 pages.
U.S. Appl. No. 11/085,325, filed Mar. 21, 2005, entitled “Memory Array Including Multiple-Gate Charge Trapping Non-Volatile Cells,” 74 pages.
U.S. Appl. No. 11/085,326, filed Mar. 21, 2005, entitled “Charge Trapping Non-Volatile Memory With Two Trapping Locations Per Gate, and Method for Operating Same,” 73 pages.
U.S. Appl. No. 11/085,300, filed Mar. 21, 2005, entitled “Charge Trapping Non-Volatile Memory and Method for Operating Same,” 73 pages.
Fujiwara,I., et al., “0.13 μm MONOS single transistor memory cell with separated source lines,” IEDM 1998, 995-998.
Chang, Kuo-Tung, et al., “A New SONOS Memory Using Source-Side Injection for Programming,” IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, 253-255.
Yeh, C.C., et al., “PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory,” IEEE IEDM, 2002, 931-934.
Sasago, Y, et al., “90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F2/bit and programming throughput of 10 MB/s,” IEEE, 2003, 4 pages.
Kobayashi, T., et al., “A Giga-Scale Assist-Gate (AG)-AND-Type Flash Memory Cell with 20-MB/s Programming Throughput for Content-Downloading Applications,” IEDM 2001, 2.2.1-2.2.4.
Naruke, K., et al., “Nonvolatile Semiconductor Memories: Technologies, design and application,” C. Hu. Ed., New York, IEEE Press, 1991, Ch. 5, pp. 183-186.
U.S. Appl. No. 11/118,839, filed Apr. 29, 2005, “Inversion Bit Line, Charge Trapping Non-Volatile Memory and Method of Operating Same”.
Tsai, Wen Jer et al., U.S. Appl. No. 10/289,866, filed Nov. 6, 2002, entitled “Erasing Method for Non-Volatile Memory,” 24 pages.
Bude, J.D., et al., “Secondary Electron Flash—a High Performance, Low Power Flash Technology for 0.35 μm and Below,” Electron Devices Meeting, 1997. Technical Digest., International, Dec. 7-10, 1997, 279-282.
Chung, Steve S., “Low Voltage/Power and High Speed Flash Memory Technology for High Performance and Reliability,” The 3rd WIMNACT—Singapore, Oct. 15, 2003, 1-48.
Chung, Steve S., et al., “A Novel Leakage Current Separation Technique in a Direct Tunneling Regime Gate Oxide SONOS Memory Cell,” Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International , Dec. 8-10, 2003 pp. 26.6.1-26.6.4.
De Blauwe, Jan, “Nanocrystal Nonvolatile Memory Devices,” IEEE Transactions on Nanotechnology, vol. 1, No. 1, Mar. 2002, 72-77.
Eitan, Boaz, et al. “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, 543-545.
Hirose, M., “Challenges for Future Semiconductor Development,” Microprocesses and Nanotechnology Conference, 2002. Digest of Papers. Microprocesses and Nanotechnology 2002. 2002 International, Nov. 6-8, 2002, p. 2-3, pluse 24 pages from outline.
Janai, Meir, “Data Retention, Endurance and Acceleration Factors of NROM Devices,” IEEE 41st Annual International Reliability Physics Symposium, Dallas, Texas, 2003, 502-505.
Lee, Chang Hyun, et al. “A Novel SONOS Structure of SiO2/SiN/Al203 with TaN Metal Gate for Multi-Giga Bit Flash Memeries,” Electron Devices Meeting, 2003. IEDM '03 Technical Digest, IEEE International, Dec. 8-10, 2003, 26.5.1-26.5.4.
Lee, Changhyun, et al., “A Novel Structure of SiO2/SiN/High k Dielectrics, Al2O3 for SONOS Type Flash Memory,” Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials. Sep. 17-19, 2002, Nagoya, 162-163.
Lee, Jae-Duk, et al., “Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation,” IEEE Electron Device Letters, vol. 23, No. 5, May 2002, 264-266.
Liu, Zhizheng et al., “A New Programming Technique for Flash Memory Devices,” International Symposium on VLSI Technology, Systems and Applications, Jun. 8-10, 1999, 195-198.
Huff, H.R. and Bevan, M., assemblers, “Questions at the International Workshop on Gate Insulators,” Ad Hoc Meeting on High-k Gate Dielectrics at the Semiconductor Interface Specialists Conference, Nov. 30, 2001, 3 pages.
Shin, Yoocheol, et al., “High Reliable SONOS-type NAND Flash Memory Cell with Al2O3 for Top Oxide,” Non-Volatile Semiconductor Memory Workshop, 2003, 2 pages.
Tsai, W.J., et al., “Data Retention Behavior of a SONOS Type Two-Bit Storage Flash Memory Cell,” Electron Devices Meeting, 2001. IEDM Technical Digest. International , Dec. 2-5, 2001 pp. 32.6.1-3
Liao Yi Ying
Tsai Wen Jer
Yeh Chih Chieh
Auduong Gene N.
Haynes Beffel & Wolfeld LLP
Macronix International Co. Ltd.
Suzue Kenta
LandOfFree
Method and apparatus for programming nonvolatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for programming nonvolatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for programming nonvolatile memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3664879