Method and apparatus for programming memory cell array

Details Method and apparatus for programming memory cell array Method and apparatus for programming memory cell array

2008-09-29

2011-10-25

Tran, Michael (Department: 2827)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185240

Reexamination Certificate

active

08045373

ABSTRACT:
Disclosed are a method and device for programming an array of memory cells.

REFERENCES:
patent: 5317535 (1994-05-01), Talreja et al.
patent: 5912837 (1999-06-01), Lakhani
patent: 5999444 (1999-12-01), Fujiwara et al.
patent: 6392928 (2002-05-01), Roohparvar
patent: 6660585 (2003-12-01), Lee et al.
patent: 6671207 (2003-12-01), Parker
patent: 6744675 (2004-06-01), Zheng et al.
patent: 6975535 (2005-12-01), Kim et al.
patent: 6980472 (2005-12-01), Ditewig et al.
patent: 7064978 (2006-06-01), Lee et al.
patent: 7085161 (2006-08-01), Chen et al.
patent: 7177977 (2007-02-01), Chen et al.
patent: 7187030 (2007-03-01), Chae et al.
patent: 7202521 (2007-04-01), Kim et al.
patent: 7262994 (2007-08-01), Fong et al.
patent: 7269072 (2007-09-01), Prall et al.
patent: 7349261 (2008-03-01), Mokhlesi
patent: 7369438 (2008-05-01), Lee
patent: 7433231 (2008-10-01), Aritome
patent: 7692961 (2010-04-01), Eitan
patent: 2001/0048612 (2001-12-01), Yi et al.
patent: 2002/0089877 (2002-07-01), Yi et al.
patent: 2006/0049451 (2006-03-01), Georgescu
patent: 2009/0080246 (2009-03-01), Jenne
patent: 2009/0323412 (2009-12-01), Mokhlesi et al.
patent: 2010/0006922 (2010-01-01), Matsuoka et al.
patent: 2010/0182831 (2010-07-01), Cernea et al.
International Search Report of International Searching Authority, dated Dec. 5, 2008 for International Application No. PCT/US08/11315; 2 pages.
International Written Opinion of International Searching Authority, dated Dec. 5, 2008 for International Application No. PCT/US08/11315; 5 pages.
Fujiwara, Ichiro, et al. “0.13 um Metal-Oxide-Nitride-Oxide-Semiconductor Single Transistor Memory Cell with Separated Source Line,” Japanese Journal of Applied Physics, vol. 39, Part 1, No. 2A, Feb. 2000, pp. 417-423.
USPTO Notice of Allowance for U.S. Appl. No. 11/904,112 dated Dec. 1, 2009; 8 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/904,112 dated Aug. 6, 2009; 7 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/904,112 dated Feb. 25, 2009; 7 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/966,631 dated Jul. 30, 2010; 4 pages.
USPTO Final Rejection for U.S. Appl. No. 11/966,631 dated Sep. 29, 2009; 7 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/966,631 dated Apr. 17, 2009; 8 pages.
USPTO Ex Parte Quayle Action for U.S. Appl. No. 11/966,631 dated Dec. 15, 2009; 4 pages.
International Search Report and Written Opinion of the International Searching Authority for International Application No. PCT/US07/20955 mailed May 5, 2008; 10 pages.
Wikipedia, the free encyclopedia, “Mosfet,” Accessed Aug. 3, 2007; 13 pages.

Affiliated with

Also associated with

Rating

Method and apparatus for programming memory cell array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for programming memory cell array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for programming memory cell array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4286628