Static information storage and retrieval – Floating gate – Disturbance control
Reexamination Certificate
2001-07-17
2002-09-10
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Disturbance control
C365S185140
Reexamination Certificate
active
06449187
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is directed to flash memory devices. In particular, the present invention is directed to flash memory devices including an array of memory cells coupled with a plurality of word lines and bit lines oriented to facilitate identifying particular cells of the array of cells. The present invention involves a treatment of such a flash memory device during programming operations in which a target cell is selected for programming by a designating word line-bit line combination. The present invention facilitates programming of the selected target cell while reducing disturbance of other cells coupled with the designating bit line that are not being programmed.
A typical flash memory cell in a flash memory array is embodied in an NMOS transistor with an integral storage element in the form of a capacitor. The storage element (i.e., the capacitor) is typically incorporated in the memory cell as a floating silicon gate sandwiched between NMOS material and a control gate. The capacitor is typically encapsulated in an oxide material to effect the required isolation to establish the necessary floating character of the storage element.
Charging and discharging the floating gate in a flash memory cell modulates the threshold voltage V
t
of the underlying NMOS transistor, and that change in threshold voltage is used as a memory state indication.
When a particular cell in a memory array is selected for programming, selection is made using a bit line-word line combination to uniquely select a particular cell. That is, a selecting bit line and a selecting word line are used to select a target cell for programming. Other cells are also coupled with the selecting word line, and other cells are coupled with the selecting bit line. These other coupled cells, not selected for programming, are subjected to some of the signals required for programming the selected target cell. Some of the programing signals, particularly those present on the selecting bit line, may disrupt programming of cells also coupled with the selecting bit line but not selected for programming. Such disruption is known by various terms in industry, including drain stress, drain disturbance and bit line stress.
There is a need for a way to reduce drain stress on cells not selected for programming yet coupled with a selecting bit line identifying a target cell for programming.
SUMMARY OF THE INVENTION
The method treats a flash memory cell array while programming a memory cell in an array having a plurality of addressable cells. The array has a plurality of bit lines coupled with at least one respective bit-coupled cell of the addressable cells. The array has a plurality of word lines coupled with at least one respective word-coupled cell of the addressable cells. Respective cells of the addressable cells are coupled with at least one word line and with at least one bit line. A respective word line-bit line combination identifies a particular cell as a target cell. Each respective cell has a drain, a source, a gate and a floating gate arrayed upon a base. The base is common to the cells. The drain, the source, the gate, the floating gate and the base cooperate to establish a floating gate-to-source electromagnetic field in each respective cell. The method includes the steps of: (a) selecting the target cell for programming by applying, in no particular order: (1) a word select programming signal to a particular word line coupled with the target cell; and (2) a bit select programming signal to a particular bit line coupled with the target cell; (b) providing at least one adjusted signal to the at least one bit-coupled cell coupled with the particular bit line to effect a decrease in strength of the floating gate-to-drain field for the at least one bit-coupled cell; (c) programming the target cell; and (d) maintaining the at least one adjusted signal at least until the programming of the target cell is complete.
The apparatus of the invention is embodied in a flash memory device configured for programming a target cell among a plurality of addressable cells arranged in an array. The array has a plurality of bit lines, each respective bit line being coupled with at least one respective bit-coupled cell, and a plurality of word lines, each respective word line being coupled with at least one respective word-coupled cell. Respective cells of the plurality of addressable cells are coupled with at least one word line and with at least one bit line. A respective word line-bit line combination identifies a particular addressable cell as the target cell. Each respective cell has a respective drain, a respective source, a respective gate and a respective floating gate arrayed upon a base. The base is common to at least some cells of the plurality of addressable cells. The respective drain, the respective source, the respective gate, the respective floating gate and the base cooperate to establish a floating gate-to-source electromagnetic field in each respective cell. A word select programming signal is applied to a particular word line coupled with the target cell, and a bit select programming signal is applied to a particular bit line coupled with the target cell. At least one adjusted signal is provided to the at least one bit-coupled cell coupled with the particular bit line. The at least one adjusted signal effects a decrease in strength of the floating gate-to-drain electromagnetic field for the at least one bitcoupled cell coupled with the particular bit line at least during programming of the target cell.
It is, therefore, an object of the present invention to provide a method and apparatus for reducing drain stress on cells in a flash memory array that not selected for programming yet are coupled with a selecting bit line identifying a target cell for programming.
Further objects and features of the present invention will be apparent from the following specification and claims when considered in connection with the accompanying drawings, in which like elements are labeled using like reference numerals in the various figures, illustrating the preferred embodiments of the invention.
REFERENCES:
patent: 5412603 (1995-05-01), Schreck et al.
patent: 5596528 (1997-01-01), Kaya et al.
patent: 5875130 (1999-02-01), Haddad et al.
patent: 5963473 (1999-10-01), Norman
patent: 6351417 (2002-02-01), Shiga et al.
Salling Craig Thomas
San Kemal Tamer
Brady III W. James
Elms Richard
Garner Jacqueline J.
Nguyen Hien
Telecky , Jr. Frederick J.
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