Boots – shoes – and leggings
Patent
1995-12-19
1997-01-21
Eng, David Y.
Boots, shoes, and leggings
3649278, 364949, 3642328, 395381, G06F 944
Patent
active
055967345
ABSTRACT:
The present invention provides a method and apparatus for programming embedded memories or on-chip caches of a variety of integrated circuits through use of the IEEE Test Access Port (TAP) architecture and logic. To accomplish this, the TAP architecture is utilized to serially shift address, data and command information into respective register chains of a RISM ACTION register located within a memory interface unit of the integrated circuit. The TAP architecture includes, among other things, a TAP port, a TAP controller and an instruction register. According to the general method used to program the embedded memories, the external system transmits a plurality of sequential signals to respective register chains of the RISM ACTION register, each sequential signal comprising an instruction specifying a write command, an address specifying a consecutive memory location within the storage means and consecutive data strings to be written to the consecutive memory locations. Next, the instruction, address and data input to the RISM ACTION register chains are transmitted in parallel to corresponding first, second and third core registers disposed within a memory unit of the integrated circuit. Upon receipt of the instruction in the first core register, an interrupt unit interrupts operation of the integrated circuit's processor and transfers processor control to executable code stored in the storage means. The executable code then writes the data stored in the third core register to the memory location specified by the address stored in the second core register in response to execution of the instruction stored in the first register.
REFERENCES:
patent: 5231314 (1993-07-01), Andrews
patent: 5237218 (1993-08-01), Josephson et al.
patent: 5311520 (1994-05-01), Raghavachari
patent: 5412260 (1995-05-01), Tsui et al.
"IEEE Standard Test Access Port and Boundary-Scan Architecture," IEEE Std. 1149.1-1990 (Includes IEEE Std. 1149.1a-1993) IEEE Computer Society, Oct. 21, 1993.
Eng David Y.
Intel Corporation
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