Method and apparatus for programming anti-fuse devices

Details Method and apparatus for programming anti-fuse devices Method and apparatus for programming anti-fuse devices

1995-02-09

1995-11-21

Westin, Edward P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Fusible link or intentional destruct circuit

326 38, H03K 19173, H03K 19082

Patent

active

054691095

ABSTRACT:
Improved apparatus and methods for programming anti-fuse devices utilized in programmable semiconductor chips are described. An anti-fuse device circuit is disclosed wherein an anti-fuse device is connected between two programming transistors, and each programming transistor is connected to a separate voltage supply bus and to a control bus network having, for example, a common control bus or separate control buses. Interconnection structures of anti-fuse devices can be formed and a targeted anti-fuse device can be programmed by connecting a programming voltage to the first associated supply bus, by connecting another voltage or ground potential to the second associated supply bus, and by turning on the appropriate control bus line or lines so that the programming transistors conduct to provide a voltage differential across the targeted anti-fuse device. Several anti-fuse device interconnection embodiments are discussed, and the choice of a particular scheme to use for fabricating a programmable chip is dependent on the desired design features and on ease of software implementation.

REFERENCES:
patent: 3271591 (1966-09-01), Ovshinsky
patent: 3629863 (1971-12-01), Neale
patent: 3699543 (1972-10-01), Neale
patent: 3987287 (1976-10-01), Cox et al.
patent: 4146902 (1979-03-01), Tanimoto et al.
patent: 4177475 (1979-12-01), Holmberg
patent: 4207556 (1980-06-01), Sugiyama et al.
patent: 4217374 (1980-08-01), Ovshinsky et al.
patent: 4226898 (1980-10-01), Ovshinsky et al.
patent: 4399372 (1983-08-01), Tanimoto et al.
patent: 4420766 (1983-12-01), Kasten
patent: 4433331 (1984-02-01), Kollaritsch
patent: 4455495 (1984-06-01), Masuhara et al.
patent: 4494220 (1985-01-01), Dumbri et al.
patent: 4499557 (1985-02-01), Holmberg et al.
patent: 4543594 (1985-09-01), Mohsen et al.
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4609998 (1986-09-01), Bosnyak et al.
patent: 4642487 (1987-02-01), Carter
patent: 4651409 (1987-03-01), Ellsworth et al.
patent: 4670749 (1987-06-01), Freeman
patent: 4691161 (1987-09-01), Kant et al.
patent: 4749947 (1988-06-01), Gheewala
patent: 4758745 (1988-07-01), Elgamal et al.
patent: 4769791 (1988-09-01), Liou et al.
patent: 4786904 (1988-11-01), Graham, III et al.
patent: 4818988 (1989-04-01), Cooperman et al.
patent: 4823181 (1989-04-01), Mohsen et al.
patent: 4855619 (1989-08-01), Hsieh et al.
patent: 4857774 (1989-08-01), El-Ayat et al.
patent: 4870302 (1989-09-01), Freeman
patent: 4873459 (1989-10-01), El Gamal et al.
patent: 4899205 (1990-02-01), Hamdy et al.
patent: 4910417 (1990-03-01), El Gamal et al.
patent: 4910418 (1990-03-01), Graham et al.
patent: 4922134 (1990-05-01), Hoffmann et al.
patent: 4924287 (1990-05-01), Orbach
patent: 4943538 (1990-07-01), Mohsen et al.
patent: 4949084 (1990-08-01), Schwartz et al.
patent: 4963770 (1990-10-01), Keida
patent: 4970686 (1990-11-01), Naruke et al.
patent: 4972105 (1990-11-01), Burton et al.
patent: 4996670 (1991-02-01), Ciraula et al.
patent: 5003200 (1991-03-01), Sakamoto
patent: 5008855 (1991-04-01), Eltoukhy et al.
patent: 5015885 (1991-05-01), El Gamal et al.
patent: 5027012 (1991-06-01), Saeki et al.
patent: 5049969 (1991-09-01), Orbach et al.
patent: 5099149 (1992-03-01), Smith
patent: 5194759 (1993-03-01), El-Ayat et al.
patent: 5200652 (1993-04-01), Lee
patent: 5223792 (1993-06-01), El-Ayat et al.
patent: 5294846 (1994-03-01), Pavinen
patent: 5341092 (1994-08-01), El-Ayat et al.
patent: 5371414 (1994-12-01), Galbraith
IBM Techical Disclosure Bulletin, vol. 19, No. 6, Nov. 1976 pp. 2144-2145.
IBM Techinical Disclosure Bulletin, vol. 19, No. 7, Dec. 1976 pp. 2628-2629.
IBM Technical Disclosure Bulletin, vol. 23, No. 6, Nov. 1980 pp. 2189-2191.
IBM Techinical Disclosure Bulletin, vol. 24, Dec. 1981, p. 3998.
Wilson et al. "A Four-Metal Layer, High Performance Interconnect System for Bipolar and BICMOS Circuits", Solid State Technology. Nov. 1, 1991 pp. 67-71.
New York Times, "Making Designer Chips On a Desktop Setup", Aug. 11, 1991.

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