Method and apparatus for programming a multi-level memory

Details Method and apparatus for programming a multi-level memory Method and apparatus for programming a multi-level memory

2009-09-24

2011-12-13

Hidalgo, Fernando (Department: 2827)

Static information storage and retrieval

Floating gate

Multiple values

C365S185010, C365S185020, C365S185110, C365S185190, C365S185220, C365S185230, C365S185240, C365S189160, C365S189150, C365S230030, C365S233160, C365S233170

Reexamination Certificate

active

08077513

ABSTRACT:
A method of programming a memory device comprising a plurality of memory cells may include verifying a first memory cell targeted to a first level with a first preliminary voltage of a first program phase (PPV1′), programming the first memory cell targeted to the first level in the first program phase, and verifying the first memory cell with a first post program-verify voltage of the first program phase (PV1′) in which the first post program-verify voltage is different from the first preliminary voltage. A corresponding apparatus is also provided.

REFERENCES:
patent: 7085168 (2006-08-01), Lee et al.
patent: 7206225 (2007-04-01), Wu
patent: 7397705 (2008-07-01), Huang et al.
patent: 7471568 (2008-12-01), Wu
patent: 7474565 (2009-01-01), Huang et al.
patent: 7474567 (2009-01-01), Lung et al.
patent: 7483299 (2009-01-01), Hsu et al.
patent: 2008/0137427 (2008-06-01), Huang et al.

Affiliated with

Also associated with

Rating

Method and apparatus for programming a multi-level memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for programming a multi-level memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for programming a multi-level memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4252988