Method and apparatus for programmable memory control with error

Details Method and apparatus for programmable memory control with error Method and apparatus for programmable memory control with error

1991-08-29

1994-05-10

Harvey, Jack B.

Excavating

371 212, G11C 2900

Patent

active

053115201

ABSTRACT:
An electronic circuit (10) for controlling and testing up to eight banks (12) of RAMs (14.sub.1 -14.sub.n) includes a controller portion (20) for controlling accessing of the RAM banks to permit read and write operations to be carried out, and for initiating testing of the RAMs as well. The circuit (10) also includes a data path portion (22) for detecting parity errors in the data written to and read from the RAMs as well as for detecting errors which occur during testing initiated by the control portion. An interface portion (24) may also be provided to allow test commands, status information and error data to be communicated to and from the circuit (10) across a four-wire boundary scan bus.

REFERENCES:
patent: 4757503 (1988-07-01), Hayes et al.
patent: 4916700 (1990-04-01), Ito et al.
patent: 4980888 (1990-12-01), Bruce et al.
patent: 5016220 (1991-05-01), Yamagata
patent: 5228045 (1993-07-01), Chiles
patent: 5231605 (1993-07-01), Lee
M. Y. Hsiao, "A Class of Optimal Minimum Odd-weight-column SEC-DED Codes," IBM J. Res. Develop., 395-401 (Jul. 1970).

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