Method and apparatus for producing n-bit outputs from an m-bit m

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364900, G06F 1300

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active

045933731

ABSTRACT:
A one-chip microcomputer system includes an arithmetic and logic unit (ALU) for processing data in an m-bit order. A random access memory is provided, which has a plurality of memory areas each of which is made of m bits. A plurality of memory areas are aligned in the horizontal direction so that the total memory bits in the horizontal direction exceeds n bits. When the row address data and the column address data are applied to an addressing circuit, a desired data of m bits is read out from the random access memory and is applied to the ALU. If only the row address data is applied to the addressing circuit, all data included in a selected row is applied to an output control circuit. The output control circuit latches n bits, whereby n-bit data is developed from the output control circuit to another electronic apparatus.

REFERENCES:
patent: 3794984 (1974-02-01), Deerfield et al.
patent: 3875391 (1975-04-01), Shapiro et al.
patent: 3938102 (1976-02-01), Morrin et al.
patent: 4090174 (1978-05-01), Voorhis

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