Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Reexamination Certificate
1999-01-29
2002-08-06
Banankhah, Majid (Department: 2156)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
C709S241000, C709S241000, C714S002000, C714S020000, C714S048000, C714S045000, C717S114000, C717S141000
Reexamination Certificate
active
06430590
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the semiconductor device simulation art. Specifically, a computer implemented method is described which is capable of automatically executing program modules having multiple execution prerequisites in a semiconductor device simulation.
The design of integrated circuits has incorporated the use of a virtual factory for simulating semiconductor device designs before any actual circuits are produced in silicon. The manufacturing process for creating circuit devices in silicon requires numerous processing steps to be taken to create a device in silicon. The virtual factory permits simulation of the devices reducing the necessity to use the actual manufacturing facilities during the design phase. Device designers can simulate components in a computer simulation facility, and conduct tests on the device to verify its performance. Thus, the designer can experiment with each device using simulation equipment which is considerably less costly than manufacturing a device using the traditional wafer processing facilities, and results are available in a few days, rather than the weeks required to form a device in silicon.
Designers have made use of these simulation systems to model a collection of processes for manufacturing devices which tend to be performance related. For instance, a single process recipe for forming a device in silicon may be altered in several ways so that a collection of devices which are related, but distinct, are modeled and tested.
The simulation includes a library of process recipes, which are stored and reused, containing executable process commands with parameters which describe the manufacturing process being simulated. Additionally, a test may be invoked for a device created with the simulated process. The entire process of creating a simulated semiconductor process to derive a simulated semiconductor device, and to test the device, creates a simulation flow. The simulation flow comprises executable modules which when executed provide an input for the simulator, which when executed by the simulator, provides an output file, indicating the performance of the device for a selected test.
The execution of the simulation has historically been done by arranging the execution modules in a simulation flow to avoid having multiple execution prerequisites for any given module. Thus, the simulation flow typically resembles a tree with leaves, so that each module execution has exactly zero or one prerequisite, permitting the use of a simplified job scheduling algorithm in a multiprocessor environment, without concern for multiple prerequisites.
However, it is advantageous in certain simulations to represent a simulation flow as executable modules in a directed acyclical graph which is a more general structure than the tree. In this well known representation, modules may have multiple prerequisites constituting an input for a module. For instance, one module may require the execution of two or more parent modules to produce the data necessary for its own execution. The prior art simulation frameworks are not known to be able to process a directed acyclic sequence graph comprising such executable modules. The present invention is directed to an automated system and method for efficient execution of modules having an execution flow represented by the more general directed acyclic graph.
SUMMARY OF THE INVENTION
The present invention provides a method to generate a simulation process representing a collection of simulated semiconductor devices and tests for the simulated devices. The semiconductor processes and tests for the simulated devices are represented by a plurality of execution modules which are automatically executed in an optimum sequence represented by a directed acyclic graph describing the module interdependencies.
The method in accordance with the invention is preferably executed in a multiprocessor system where each execution module is farmed out by a supervisory processor to an available processor for execution. The execution module is implemented as a directory containing a file of pointers to identify any parent module which must be executed first, and may include pointers to any child modules which are subsequently executed. The directory also includes a status file to indicate the execution state of each module. During a simulation of the collection of semiconductor processes and testing of the simulated devices, a supervisory processor of the multiprocessor system initiates execution of the modules in an order defined by the identity of any parent pointers contained within the directory. Once an execution module has completed execution, a command within the execution module changes the status file of the directory to indicate the execution has completed.
The file of pointers for each execution module permits the supervisory processor to maintain a list of those modules which are parent modules, and execution for any such child module is delayed until the parent module is executed. When the module is ready for execution, the supervisory processor provides job farming of the execution module to an available processor.
The invention may advantageously be stored as a set of instructions on a computer readable medium which is used to program the supervisory processor to carry out the inventive method.
REFERENCES:
patent: 5331579 (1994-07-01), Maguire, Jr. et al.
patent: 5826078 (1998-10-01), Funaki
patent: 5889999 (1999-03-01), Breterniz, Jr. et al.
patent: 6026365 (2000-02-01), Hayashi
patent: 6230200 (2001-05-01), Forecast et al.
Banankhah Majid
Connolly Bove & Lodge & Hutz LLP
LandOfFree
Method and apparatus for processing executable program... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for processing executable program..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for processing executable program... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2897777