Image analysis – Image enhancement or restoration – Image filter
Reexamination Certificate
1998-08-05
2001-05-29
Lee, Thomas D. (Department: 2724)
Image analysis
Image enhancement or restoration
Image filter
C382S283000
Reexamination Certificate
active
06240216
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an image processing method and, more particularly, to mask processing (noise reduction, smoothing of a pattern or the like) of binary image data by software.
BACKGROUND OF THE INVENTION
With the wide spread use of Internet (World Wide Web) and/or the increased demands for handling of image data due to users' multimedia-oriented inclinations, it is required to process image data at high speed.
However, an image may be subject to deterioration and a noise may be generated by an image inputting phase (e.g., receipt of a scanner input, FAX data from a public telephone line, an input from a digital camera) and by an image processing phase (e.g., an analog/digital conversion, an image compression/decompression process). Also, in case of enlarging a pattern such as an inputted small character, a resultant pattern having a large corner that is not represented by a smooth curve may be generated.
Such an image including a deteriorated pattern appears ungainly to a user and it becomes sometimes unrecognizable. Also, in case of subsequently performing pattern recognition (e.g., character or graphic recognition), it causes a problem such as degradation of a recognition rate and/or increase of processing time to occur.
In order to solve the problem of prior art, another Japanese patent application (H8-42302), filed on Feb. 29, 1996, by the assignee of the present application, which is not publicly available at the filing date the present application, proposes a method of performing a smoothing process at high speed by using only SHIFT, logical NOT, AND, OR operations of bit strings, without recourse to conditional tests in the form of “IF THEN ELSE” and “SWITCH” statements that have been required in the conventional image process using a mask. However, because this prior method is limited to processing of an image with a specific horizontal size (width) such as 8/16/32/64 bits or the like due to a length of a processing unit or a register, it is now desired to provide an improved method that may be applied to an image with an arbitrary size.
It is, therefore, an object of this invention to improve a processing speed in smoothing a graphic outline.
It is another object of this invention to enable application of a high speed image process using a mask, which is adapted for noise reduction and/or smoothing of an enlarged image, to a binary image with an arbitrary size.
It is another object of this invention to provide a pattern (character or graphic) recognition system that has a high recognition rate.
BRIEF DESCRIPTION OF THE INVENTION
In case of performing a mask process such as smoothing for a graphic or a character of a binary image drawn into a bit pattern, it is contemplated to use only SHIFT, logical NOT, AND, OR operations of bit strings, rather than using conditional branch instructions in the form of “IF THEN ELSE” and “SWITCH” statements that lead to undesirable reduction of processing speed. In so doing, this method enables a substantial increase in the processing speed.
Further, in order to process an image that is wider than a bus width or a register length at high speed, adjacent patterns of an original image, which are not necessarily used for a logical operation, are loaded onto left and right sides of a processing object, such that this is used as a processing unit in an operation. Then, as a processed result, the part of the processing object is outputted.
In accordance with one aspect of this invention, there is provided a method of processing an image of a bit pattern, which is “m” bits wide and “n” lines high (“m” and “n” are natural numbers), by using a computer system having an operation storage area of an “r” bit width (“r” is a natural number), comprising the steps of:
(a) extracting from a current “i”th line (“i” is a natural number less than or equal to “n”) of said bit pattern, a processing unit of “t” bits (“t” is a natural number less than or equal to “m” and “r”) including a current processing object of “s” bits and a pair of “a” bits (“a” is a natural number), each immediately preceding and succeeding said current processing object respectively, and storing said processing unit into said operation storage area;
(b) performing logical operations by using three line variables, including said current processing object, an upper processing object of “s” bits located on an upper “i−1”th line at the same columns as said current processing object, and a lower processing object of “s” bits located on a lower “i+1”th line at the same columns as said current processing object, as well as six line variables each being formed by bit-shifting each of said current, upper and lower processing objects to the left and right respectively:
(c) outputting “s” bits including a result of said logical operations as a processed result; and
(d) repeating said steps (a) through (c) by using “s” bits that consecutively succeed said current processing object as a new current processing object.
Note here that, in the claims of the present specification, the expression “operation storage area” represents a concept covering a register.
In accordance with another aspect of this invention, there is provided a method of processing an image of a bit pattern, which is “m” bits wide and “n” lines high (“m” and “n” are natural numbers), by using a computer system having an operation storage area of an “r” bit width (“r” is a natural number), comprising the steps of:
(a) extracting from a current “i”th line (“i” is a natural number less than or equal to “n”) of said bit pattern, a processing unit of “t” bits (“t” is a natural number less than or equal to “m” and “r”) including a current processing object of “s” bits and a pair of “a” bits (“a” is a natural number), each immediately preceding and succeeding said current processing object respectively, and storing said processing unit into said operation storage area;
(b) performing logical operations by using bits included in said “a” bits and said current processing object;
(c) outputting “s” bits including a result of said logical operations as a processed result; and
(d) repeating said steps (a) through (c) by using “s” bits that consecutively succeed said current processing object as a new current processing object.
In accordance with another aspect of this invention, there is provided a method of processing an image of a bit pattern, which is “m” bits wide and “n” lines high (“m” and “n” are natural numbers), by using a computer system having an operation storage area of an “r” bit width (“r” is a natural number), comprising the steps of:
(a) extracting from a current “i”th line (“i” is a natural number less than or equal to “n”) of said bit pattern, a processing unit of “t” bits (“t” is a natural number less than or equal to “m” and “r”) including a current processing object of “s” bits along with “a1” bits immediately preceding said current processing object and “a2” bits immediately succeeding said current processing object (“a1” and “a2” are natural numbers), and storing said processing unit into said operation storage area;
(b) performing logical operations by using bits included in said “a1” bits, said “a2” bits and said current processing object;
(c) outputting “s” bits including a result of said logical operations as a processed result; and
(d) repeating said steps (a) through (c) by using “s” bits that consecutively succeed said current processing object as a new current processing object.
In accordance with another aspect of this invention, there is provided a method of processing an image of a bit pattern, which is “m” bits wide and “n” lines high (“m” and “n” are natural numbers), by using a computer system having an operation storage area of an “r” bit width (“r” is a natural number), comprising the steps of:
(a) extracting from a current “i”th line (“i” is a natural number less than or equal to “n”) of said bit pattern, a processing unit of “t” bits (“t” is a natural number less than or equal to “m” and “r”) including a current processing object of “s” bits and a pai
Nemoto Naoyuki
Takahashi Hiroyasu
Brinich Stephen
International Business Machines - Corporation
Lee Thomas D.
Tassinari, Jr. Robert P.
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