Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-02-25
2004-10-19
Zarneke, David A. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090, C438S015000
Reexamination Certificate
active
06806725
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method and apparatus for the handling of arrays of electronic devices, and in particular to the testing and marking of such electronic devices for subsequent processing after they have been electrically separated. The electronic device may be any one of a variety of devices, including but not limited to, a chip on a wafer, a chip scale package (CSP) or chip scale ball grid array (CSBGA) package.
BACKGROUND AND PRIOR ART
The growth of and the demand for miniaturization of consumer electronics (especially portable electronics equipment) has consistently required the reduction of the size of semiconductor packages, while concurrently, die components are becoming denser and pin count of each die is increasing. The drive to achieve increased integrated circuit (IC) capability inside a smaller package has resulted in the development of chip-scale packages (CSP). These new smaller devices are gaining acceptance and the back-end assembly and test infrastructure is consequently coping to meet the challenges of handling and processing these small devices.
Meanwhile, we are seeing the rapid adoption of chip-scale packages such as fine-pitch ball grid array (FBGA) and micro leadframe packages (MLP), which are defined by the package size being no more than 20% larger than the size of the die. The challenges presented by chip-scale packages at the test-stage are primarily in the areas of fixturing and handling.
In a typical semiconductor device manufacturing process called front-end processing, a plurality of integrated circuits is formed on a wafer, such as a silicon wafer. Once the integrated circuits are formed, the wafer is diced into individual chips. The front-end processing of semiconductor devices requires probing to identify the correctly-formed devices and to ink-mark the defective devices. These chips are then packaged for the next assembly line, referred to as back-end processing. Devices inked as defective will be sorted out and only those devices that are correctly-formed will proceed to the next process.
The formation of IC components requires numerous individual process operations, primarily in front-end processing, which are performed in a specific sequence, as known in the art. Each of these operations must be precisely controlled and monitored so that the IC components operate with the required electrical characteristics. However, even though the operations are precisely controlled and monitored, IC component failures still occur. Thus, it is important to detect the defective IC components as early as possible to prevent the unnecessary expense of continuing the fabrication of any defective electronic devices.
The IC components are generally tested after they are fabricated on the wafer and just prior to dicing the wafer into individual chips. These chips are then assembled during back-end processing by electrically connecting the individual pads of the chip to the electrical traces on the substrate for FBGA and at the individual electrical paths on the lead-frame for MLP. The process is known as wire bonding. Typically, 25 &mgr;m diameter gold wire is used. The next step in the process is to protect the device from the outside world, by panel-molding the substrate of the electronic device with a laser-markable plastic molding compound, such as that described in U.S. Pat. No. 4,753,863.
The next sequence in the process is to isolate the electronic devices electrically by singulating them into individual electronic devices and then testing them.
Currently, IC chips are often tested and marked individually after singulation. The testing and marking process is difficult and delicate if a typical method of testing the electrical characteristics of the electronic devices after they are formed is used. Such a typical test requires physical contact with the device's individual input and output leads or signal paths. There is a need to reduce processing time and costs by minimizing the individual handling of singulated electronic devices.
The physical contact required for testing generally comprises contacting a plurality of individual balls or pads on an electronic device with a plurality of test contacts housed in the test contactor housing. The test contacts are usually fabricated from metal material and reside in vias that extend into the contactor housing. The test contacts may be biased by a spring mechanism. The test contacts are each in electrical contact with a device interface board within the contactor housing, which directs electrical test signals to the electronic device. The test contacts extend out of the contactor housing vias to contact the electronic device's balls or pads.
The test is not reliable unless the devices are separated electrically. However, to separate them electrically will require them to be separated physically by sawing or other singulation means. The difficulty is to test the electronic devices individually at the testing stage and to identify each individual device as “failed” or “passed” without slowing down the process. Electronic devices on a tape within a wafer ring can be tested for specific electrical characteristics by sending and/or receiving signals through the test contacts. The electronic devices that fail the test procedure are “mapped” such that when an array of devices is diced, the failed electronic devices will not be picked up for packing and can be culled.
Conventional back-end assembly typically comprises many independent processes or if the process is mechanized, it is a process dedicated for particular equipment. Die Bond, Wire Bond, Molding, Ball Placement, Marking, Sawing, and Test and Packing are examples of separate processes and equipment. Conventional back-end assembly and test processing are not favorable for manufacturing small electronic devices. The manufacture of these devices requires full automation processing. Automating and integrating some of the processes and equipment will be beneficial as to profitability and efficiency. Cost reduction is also one of the direct results of automation and integration. Performing functions en masse, rather than one at a time, has always been a method of reducing costs. However, to do so, an innovative system that will provide the means to handle seamless mass manufacturing should be developed. To meet the needs of this new packaging process, an integrated mechanization of singulation, test and marking is required.
SUMMARY OF THE INVENTION
With the foregoing background in mind, it is an object of this invention to provide for test handling electronic devices using a method and an apparatus that can effectively handle an array of electronic devices substantially simultaneously.
It is a further object of the present invention to improve the handling of an array of small electronic devices and increase the productivity of testing, inscribing and collecting electrical devices.
According to one aspect of the invention there is provided a method of processing an array of electronic components comprising the steps of providing mounting means mounting unsingulated electronic components onto the mounting means, singulating the components to physically separate them, and testing the singulated electronic components for defects whilst they are mounted on the mounting means and without removal therefrom.
According to a second aspect of the invention there is provided an apparatus for processing an array of electronic components comprising mounting means for mounting electronic components, a singulating device for singulating the said array of electronic components and a testing device for testing each of the said components for defects, whereby singulation and testing of electronic components are conducted while they are mounted on the mounting means without removal therefrom.
It will be convenient hereinafter to describe the invention in greater detail by reference to the accompanying drawings which illustrate one embodiment of the invention. The particularity of the drawings and the related description is not to be understo
Chow Lap Kei Eric
Curito, Jr. M. Bilan
Tsui Ching Man Stanley
ASM Assembly Automation Ltd.
Ostrolenk Faber Gerb & Soffen, LLP
Patel Paresh
Zarneke David A.
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