Method and apparatus for processing a predicated instruction...

Details Method and apparatus for processing a predicated instruction... Method and apparatus for processing a predicated instruction...

2005-04-19

2005-04-19

Treat, William M. (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

C712S214000, C712S217000

Reexamination Certificate

active

06883089

ABSTRACT:
A system and method of processing a predicated instruction is disclosed. A consumer instruction and a predicated instruction are received in an reservation station of an out-order processor. The consumer instruction depends on a result of the predicated instruction. The predicated instruction is dispatched to an execution unit for execution. The executed predicate instruction is stored in a re-order buffer.

REFERENCES:
patent: 6513109 (2003-01-01), Gschwind et al.
Becker et al., “The PowerPC 601 Microprocessor”, Micro, IEEE, vol. 13, iss. 5, Oct. 1993, pp. 54-68.*
Perry Wang, et al.,Register Renaming and Scheduling for Dynamic Execution of Predicated Code, (electronic version) The Seventh IEEE International Symposium on High Performance Computer Architecture, Jan. 20-24, 2001, pp. 1-11, Monterrey, Mexico, IEEE Computer Society, ISBN 0-7695-1019-1.

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