Method and apparatus for preventing recursion jeopardy

Details Method and apparatus for preventing recursion jeopardy Method and apparatus for preventing recursion jeopardy

1990-01-05

1992-05-19

Shaw, Dale M.

395775, G06F 1300

Patent

active

051155060

ABSTRACT:
A microprocessor including unprime registers for use during normal operation, prime registers for use during interrupts, a normal register set for use during normal operation and conventional interrupt operations, an alternate register set for use during fast interrupt operations, and a memory stack. Three status bits are used to indicate that one or more fast interrupts have been initiated but not completed, that a fast interrupt is occurring but there are no other fast interrupts being processed, and that the CPU is currently processing a fast interrupt. These status bits indicate if there is a recursion jeopardy and are used to control the flow of information between the normal and alternate register sets and the memory stack in order to prevent recursion.

REFERENCES:
patent: 3858182 (1974-12-01), Delagi et al.
patent: 4217638 (1980-08-01), Namimoto et al.
patent: 4410939 (1983-10-01), Kawakami
patent: 4434461 (1984-02-01), Puhl
patent: 4812967 (1989-04-01), Hirosawa
patent: 4905196 (1990-02-01), Kirmann
"A Programmer's View of the 80960 Architecture", S. McGeady, Intel Corp., Hillsboro, OR.

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