Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2005-02-08
2005-02-08
Phung, Anh (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185140, C365S185280
Reexamination Certificate
active
06853583
ABSTRACT:
Methods and apparatuses prevent overtunneling inpFET-based nonvolatile floating gate memory (NVM) cells. During a tunneling process, in which charge carriers are removed from a floating gate of apFET-based NVM cell, a channel current of a memory cell transistor is monitored and compared to a predetermined minimum channel current required to maintain a conducting channel in an injection transistor of the memory cell. When the monitored channel current drops below the predetermined minimum channel current, charge carriers are injected onto the floating gate by impact-ionized hot-electron injection (IHEI) so that overtunneling is avoided.
REFERENCES:
patent: 5596524 (1997-01-01), Lin et al.
patent: 5617358 (1997-04-01), Kodama
patent: 5627392 (1997-05-01), Diorio et al.
patent: 5736764 (1998-04-01), Chang
patent: 5754471 (1998-05-01), Peng et al.
patent: 5761121 (1998-06-01), Chang
patent: 5763912 (1998-06-01), Parat et al.
patent: 5825063 (1998-10-01), Diorio et al.
patent: 5898613 (1999-04-01), Diorio et al.
patent: 5969987 (1999-10-01), Blyth et al.
patent: 5990512 (1999-11-01), Diorio et al.
patent: 6028789 (2000-02-01), Mehta et al.
patent: 6137721 (2000-10-01), Kalnitsky et al.
patent: 6137722 (2000-10-01), Kalnitsky et al.
patent: 6137723 (2000-10-01), Bergemont et al.
patent: 6137724 (2000-10-01), Kalnitsky et al.
patent: 6222771 (2001-04-01), Tang et al.
patent: 6294810 (2001-09-01), Li et al.
patent: 6385090 (2002-05-01), Kitazaki
patent: 0 778 623 (1997-06-01), None
Diorio, “A p-Channel MOS Synapse Transistor with Self-Convergent Memory Writes”, IEEE Transactions On Electron Devices, vol. 47, No. 2, pp. 464-472, Feb. 2000.
Lanzoni et al., “A Novel Approach to Controlled Programming of Tunnel-Based Floating-Gate MOSFET's”, 1994, IEEE Journal of Solid-State Circuits, vol. 29, pp. 147-150.
International Search Report dated Jan. 20, 2004, for Application No. PCT/US03/23724.
Diorio Christopher J.
Gilliland Troy
Lindhorst Chad
Pesavento Alberto
Srinivas Shail
Impinj, Inc.
Phung Anh
Ritchie David B.
Thelen Reid & Priest LLP
Winters William E.
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