Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1998-12-10
2000-05-23
Powell, William
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438734, 438743, 148 333, H01L 2100
Patent
active
06066570&
ABSTRACT:
A method for increasing chip yield by reducing black silicon deposition in accordance with the present invention includes the steps of providing a silicon wafer suitable for fabricating semiconductor chips, depositing a first layer over an entire surface of the wafer, removing a portion of the first layer to expose a region suitable for forming semiconductor devices and etching the wafer such that a remaining portion of the first layer prevents redeposition of etched material on the wafer. A semiconductor assembly for reducing black silicon deposition thereon, includes a silicon wafer suitable for fabricating semiconductor chips, the wafer having a front surface for forming semiconductor devices, a back surface and edges. A deposited layer is formed on the wafer for covering the back surface and the edges such that redeposition of silicon on the back surface and edges of the wafer during etching is prevented.
REFERENCES:
patent: 4925809 (1990-05-01), Yoshiharu et al.
patent: 5494849 (1996-02-01), Iyer et al.
Dobuzinsky David M.
Perng Dung-Ching
Roithner Klaus
Wang Ting Hao
International Business Machines - Corporation
Paschburg Donald B.
Powell William
Siemens Aktiengesellschaft
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