Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1998-12-28
2001-01-09
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S693000, C438S928000
Reexamination Certificate
active
06171873
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor chip manufacture and more particularly to the prevention of chip breakage during manufacturing process steps.
2. Background Description
The production of an individual semiconductor device involves four stages prior to assembly into an electronic component, as shown in prior art FIG.
1
.
The first stage is front end of line (FEOL
11
), in which dopants and materials are implanted into, or deposited onto, the semiconducting material—usually silicon—of the substrate wafer and heat treated. The FEOL
11
generates many individual logic gates, memory cells or other discrete circuit elements over the wafer surface.
The next stage is back end of line (BEOL
12
), in which successive layers of conductors and insulators are deposited onto the wafer to make a three-dimensional structure interconnecting the individual elements. The BEOL
12
generates very-large-scale integrated (VLSI) circuits patterned in a rectangular array over the wafer as individual devices. After BEOL
12
processing the VLSI devices are probed or tested
13
for speed or quality and a map
14
is generated of the electrical performance of the devices on the wafer.
The third stage, wafer finishing, consists of two sub-stages: back-side grind (BSG
15
) and dice, sort and pick (DSP
16
). In the BSG
15
operation the wafers are ground on the back (non-device) side using a grinding wheel to generate a wafer of appropriate thickness and back-side surface finish. In the DSP
16
operation the individual devices (dice or chips) are separated via a dicing or sawing operation along the intervening scribe lines and then picked from the structure used to support the wafer during the dicing operation, using
17
the performance map
14
created at the end of the BEOL
12
stage to sort the picked chips for placement in containers suitable for packaging operations.
The fourth and final stage is packaging (PKG
18
), in which an individual chip is mounted onto a larger carrier, electrical connections are made between the chip and the electrical circuitry of the carrier, and then the whole finally sealed or encapsulated and tested. The mechanical yield and reliability of a finished device is determined by the mechanical performance of the chip, set during the BSG
15
and DSP
16
stages.
Improper FEOL
11
or BEOL
12
processing or electrical mis-sorting during DSP
16
leads to devices that fail to perform with the appropriate electrical characteristics. Analogously, improper BSG/DSP/PKG processing or mechanical mis-sorting or non-sorting leads to devices that fail mechanically. Many PKG
18
schemes impose significant stresses on the contained die (i.e. the chip which has been diced from a wafer in the manufacturing process), the most damaging being tensile stresses leading to fracture of the brittle semiconducting material. The strength of the chips is critical to acceptable mechanical yield during and after PKG
18
, just as appropriate FEOL
11
and BEOL
12
processing is critical to acceptable electrical yield prior to wafer finishing. Obviously, greater strength chips are more resistant to fracture and can therefore lead to smaller yield losses and greater reliability. The strength of a die set by the BSG
15
and DSP
16
operations can be enhanced by attention to these operations, but usually at the expense of increased processing time and increased cost.
Currently, in contrast to the electrical performance, no sorting is done of the mechanical strength of a die to match it to the requirements set by the PKG
18
stress. For example, turning to prior art
FIG. 3
, mounting of a chip onto a metallic leadframe
31
(
FIG. 3A
) imposes greater tensile stress
34
on the backface of the chip than the tensile stress
35
from mounting onto a fiberglass-polymer composite laminate
32
(FIG.
3
B), which in turn imposes greater stress
36
than does mounting onto a ceramic substrate
33
(FIG.
3
C). A lack of mechanical sorting would lead to increasing yield loss at the packaging stage PKG
18
, for use of substrates made of ceramic, polymer composite, and metal, respectively. All yield losses could be reduced to a minimum by sorting the highest strength chips into the highest stress packages.
SUMMARY OF THE INVENTION
It is therefore an object of the present-invention to sort the highest strength chips into the highest stress packages, thereby avoiding the sorting of low-strength chips into high-stress packages.
It is also an object of the invention to classify chips according to their tensile or bending strength by direct inspection of the orientation of grinding striations on the backside of a chip.
It is a further object of the invention to provide finishing methods that allow all chips on a backside-ground wafer to exceed a given strength level.
Another and related object of the invention is to set the strength level by controlling the wafer and grinding wheel or belt geometries.
An additional object of the invention is to allow backside-ground chips to be classified by strength at the wafer level, without inspection, permitting a map of mechanical peformance to be overlayed on that of electrical performance and therefore allow devices to be picked and sorted for various applications and packaging schemes.
A related object of the invention is to create a mechanical performance map from knowledge of the wafer, chip and grinding wheel geometries.
The invention uses a relation between striation orientation and chip strength and provides a method for classifying chips according to their tensile or bending strength by direct inspection of the orientation of grinding striations on the backside of a chip. It provides finishing methods that allow all chips on a backside-ground wafer to exceed a given strength level. Another aspect of the invention is that the strength level can be set by controlling the wafer and grinding wheel or belt geometries.
The invention provides sorting methods that allow backside-ground chips to be classified by strength at the wafer level, without inspection, permitting a map of mechanical peformance to be overlayed on that of electrical performance and therefore allows devices to be picked and sorted for various applications and packaging schemes. A feature of these methods is that the mechanical performance map can be created from knowledge of the wafer, chip and grinding wheel-geometries.
REFERENCES:
patent: 4652757 (1987-03-01), Carver
patent: 4654681 (1987-03-01), Jastrzebski
patent: 4663890 (1987-05-01), Brandt
patent: 4900363 (1990-02-01), Brehm et al.
patent: 4968628 (1990-11-01), Delgado et al.
patent: 5162241 (1992-11-01), Mori et al.
patent: 5677001 (1997-10-01), Wang et al.
patent: 6054369 (2000-04-01), Neilson et al.
patent: 6110391 (2000-08-01), Takei et al.
patent: 6116988 (2000-09-01), Ball
Blondin John M.
Brouillette Donald W.
Cook Robert Francis
Diefenderfer David Frederick
Liniger Eric Gerhard
Booth Richard
International Business Machines - Corporation
Leas James M.
McGuireWoods LLP
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