Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1999-01-27
2002-04-23
Frejd, Russell W. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S022000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06377909
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for preparing a logic simulation model used in circuit verification of a semiconductor device.
2. Description of Related Art
In a circuit design of a semiconductor device, it is necessary to carry out a logic simulation at a design stage for verifying whether or not the logic of the circuit operates normally. In order to perform the logic simulation on an actual hardware model, a restriction occurs in a modeling. Therefore, a logic simulation is carried out at a high speed by preparing a software model described with object codes representing an operation of the logic circuit precisely in logic and in timing, and by executing the software model.
As a method for preparing this type of software logic simulation model, for example, Japanese Patent Application Pre-examination Publication No. JP-A-08-263530 proposes a logic simulation model preparing method capable of extracting logic information and delay information from a verified logic circuit, and preparing a model which has an optimized logical representation and is equivalent in logic simulation to an original logic circuit and which can be simulated at a high speed.
However, if a circuit scale becomes large, this method becomes to requires a great deal of time and labor in order to verify the whole of the circuit. Therefore, it is common to retain, as a library in units of block, circuit blocks that have been confirmed to be normal after a first verification is executed, and to use the verified circuit blocks without modification at the time of designing a new circuit, thereby to shorten the time for verification. In this case, a logic equivalent to the logic represented by the verified circuit block is logically expressed by means of software, and the whole of the logic circuit is logically simulated.
Now, the above mentioned prior art method for preparing the logic simulation model will be described with reference to FIG.
16
.
First, a logic synthesis is carried out on the basis of a logic design data base
102
and verified logic circuits
101
by means of a logic synthesis section
1619
.
In the logic synthesis section
1619
, first, a function of logic gates included in the verified logic circuits
101
is extracted from the logic design data base
102
(step
103
), and then, the logic gates are connected in accordance with connection information to prepare a logic network (step
104
). Furthermore, a FFR (fanout free region) division is executed for a combinational circuit included in the logic circuit.
Here, the FFR division means to analyze a connection relation in the combinational circuit and to divide the combinational circuit in a place where a signal line is fanned out
Thereafter, a two-step logicizing is performed in which the logical expression is converted into an expression using a two-step logic of an AND and an OR (step
106
), and finally, a logic optimization is carried out (step
1607
). Thus, a logic network
1601
constituted of optimized combinational circuits and sequential circuits is obtained.
Here, the logic optimization means to convert a given logical expression into a logical expression having a minimum number of operations.
Next, the processing of the two-step logicizing (step
106
) and the processing of the logic optimization (step
1607
) will be described in detail on a specific example with reference to FIG.
17
.
Here, explanation will be made on the case of logically optimizing a logic circuit shown in FIG.
18
. The logic circuit of
FIG. 18
executes a logical operation for three inputs A, B and C, and obtains one output Y.
The logic function
201
of the FFR divided in the step
105
is first developed into minterms so that a cube list
203
is prepared (step
202
) Here, the “cube” means a term in a logical expression.
If the logic circuit shown in
FIG. 18
is expressed in a two-step-logicized logical expression, the logical expression can be expressed as the equation (1) shown in FIG.
18
. Here, “ABC” indicates a logical AND of “A”, “B” and “C”. An upper bar given to a character indicates an inversion, and “+” means a logical OR.
This logical expression is prepared as the cube list
203
. The Karnaugh map
215
shows this logical expression.
Next, main terms are generated from the logical expression included in the cube list
203
, and are stored as a main term table
205
(step
204
).
Then, only indispensable terms are selected from the main terms, and selected cover conditions
207
are stored in a cover table
207
(step
206
). The Karnaugh map
217
shows the indispensable terms. There are a plurality of methods for selecting the indispensable terms from the main terms. The “cover” indicates which of the main terms is selected as an indispensable term.
By obtaining the logical OR of the indispensable terms, a minimum logical-OR form
208
is obtained as shown in a logical expression
218
.
Finally, this minimum logical-OR form
208
is converted into a truth table
219
in the form of a cube expression, and stored as a logic network
1601
(step
209
).
Next, by using the logic network
1601
, a LCC (levelized compiled code) processing precedence is determined (step
1602
).
In a logic circuit having no need of considering a delay, a final result of the logic circuit can be obtained by operating each of gate circuits that constitute that logic circuit, one time.
And, a method for determining the precedence for operating the respective gate circuits is an LCC analysis. In the prior art, this LCC analysis could be applied only to analysis of a logic constituted of only combinational circuits. A method for making it possible to apply the LCC analysis to a sequential circuit by giving a condition to the circuit, is described in Japanese Patent Application No. 165341/1997 (Japanese Patent Application Pre-examination Publication No. JP-A-10-340291).
A delay information generator
116
extracts timing information from the logic circuit information in the verified logic circuits
101
. Then, a static delay analysis is carried out (step
120
) and an input-to-output delay is calculated (step
121
). Thus, a hash table
117
and a delay data base
118
can be obtained.
The hash table
117
is provided for a high speed retrieval of the delay data base
118
by using the name and the value of an input terminal and an output terminal, as a key.
Finally, the program code is optimized by a general purpose compiler, so that a simulation model object code
115
is prepared (step
1603
).
In the prior art method for preparing the logic simulation model, at the time of optimizing the program code, the general purpose compiler independently analyzes the program similarly to an analysis of an ordinary program.
For example, in an example of the optimization of the program code, an optimizing compiler analyzes the program for the program-coded simulation mode, and collects information as to where the logical operation and the load/store of the variable values are executed in the program, and then, omits unnecessary codes.
This optimization of the program code in the prior art method for preparing the logic simulation model will be specifically described with reference to FIG.
19
.
A program code (before optimization)
511
is one obtained by converting some logical expressions FFR
1
and FFR
2
into program codes. In this program code, it has been determined by the LCC processing precedence determination in the step
1602
that the logical expression FFR
1
is executed prior to the logical expression FFR
2
.
In this analysis of the general purpose compiler, since both the operation of obtaining “r3” from “r1” and “r2” and the operation of obtaining “r13” from “r11” and “r12” are executed by the operation of “x1·x2”, program codes
510
become unnecessary by omitting the operation executed later and by substituting “r3” for “r13”, with the result that the number of operations can be reduced.
As mentioned above, the program code
511
is analyzed and optimized by the general purpose compiler s
Frejd Russell W.
NEC Corporation
Scully Scott Murphy & Presser
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