Method and apparatus for preforming memory segment limit violati

Details Method and apparatus for preforming memory segment limit violati Method and apparatus for preforming memory segment limit violati

1994-05-02

1996-11-19

Lane, Jack A.

3954211, G06F 9355, G06F 1206

Patent

active

055772196

ABSTRACT:
A method and apparatus for determining if an effective address for a memory access in a computer processor is above an expand-down memory segment. The apparatus comprises a memory segment limit comparison circuit. The segment limit comparison circuit tests every memory access to determine if the memory access reaches above the top limit of an expand-down memory segment. The comparison circuit consists of an adder that adds an effective address of the memory access to an access.sub.-- size value. The access.sub.-- size value consists of the size of the memory access to be performed minus one in the low order bits and a series of "1" bits in the high order bits necessary to generate a carry if the memory access reaches above the top limit of the expand-down memory segment.

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