Method and apparatus for preforming DCT and IDCT transforms on d

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364DIG1, 364DIG2, 3642604, 364725, G06F 1714

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active

054524660

ABSTRACT:
A method and apparatus for implementing a discrete cosine transform (DCT) or an inverse DCT (IDCT) with a single hardware unit which applies only positive valued multiplicative coefficients and can be switched to either perform a DCT or an IDCT. The invention processes parallel input digital data signals to produce parallel output digital data signals which represent a discrete transform (either a DCT or an IDCT) of the input data. One aspect of the invention is a method and apparatus for performing discrete transforms using a multiplier which implements MSB-first, bit-serial, carry-save, multiplication of an input word by a positive fixed coefficient. In one class of embodiments, the serially received digits of the input word can take on positive values only. In other embodiments, the serially received digits of the input word can take on positive or negative values. Performance of MSB-first carry-save multiplication allows the design of extremely efficient transforming hardware having low processing delay and high precision, and supporting medium to low speed transform rates. Another aspect of the invention is a method and apparatus for performing discrete transforms using a butterfly addition/subtraction circuit which receives two serial signals and generates both the sum and difference of such signals. In one class of embodiments, the inventive butterfly addition/subtraction circuit implements MSB-first, bit-serial addition and subtraction. In other embodiments, the inventive butterfly addition/subtraction circuit implements LSB-first, bit-serial addition and subtraction.

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Hsieh S. Hou, "A Fast Recursive Algorithm For Computing the Discrete Cosine Transform," IEEE Transactions on Acoustics, Speeches and Signal Processing, vol. ASSP-35, No. 10, pp. 1455-1461 (Oct. 1987).
Jutand, et al., "A 13.5 MHz Single Chip Multiformat Discrete Cosine Transform," SPIE, vol. 845, Visual Communications and Image Processing II, pp. 6-12 (1987).
Demassieux, et al., "An Optimized VLSI Architecture for a Multiformat Discrete Cosine Transform," ICASSP 87, pp. 547-550 (1987).
Mou, et al., "A High-speed Low-cost DCT Architecture for HDTV Applications," ICASSP 91, pp. 1153-1156 (1991).
Noll, "2.1 Semi-systolic Maximum Rate Transversal Filter with Programmable Co-efficients," Internatioanl Workshop on Systolic Arrays, pp. 103-112 (1986).

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