Electrical computers and digital processing systems: processing – Instruction fetching – Prefetching
Reexamination Certificate
2011-03-29
2011-03-29
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction fetching
Prefetching
Reexamination Certificate
active
07917731
ABSTRACT:
A processor performs a prefetch operation on non-sequential instruction addresses. If a first instruction address misses in an instruction cache and accesses a higher-order memory as part of a fetch operation, and a branch instruction associated with the first instruction address or an address following the first instruction address is detected and predicted taken, a prefetch operation is performed using a predicted branch target address, during the higher-order memory access. If the predicted branch target address hits in the instruction cache during the prefetch operation, associated instructions are not retrieved, to conserve power. If the predicted branch target address misses in the instruction cache during the prefetch operation, a higher-order memory access may be launched, using the predicted branch instruction address. In either case, the first instruction address is re-loaded into the fetch stage pipeline to await the return of instructions from its higher-order memory access.
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Sartorius Thomas Andrew
Smith Rodney Wayne
Stempel Brian Michael
Chan Eddie P
Kamarchik Peter M.
Pauley Nicholas J.
Qualcomm Incorporated
Velasco Jonathan
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