Method and apparatus for predicting valid performance of virtual

Details Method and apparatus for predicting valid performance of virtual Method and apparatus for predicting valid performance of virtual

1988-07-25

1993-01-12

Shaw, Gareth D.

Boots, shoes, and leggings

364DIG1, 36423221, 3642563, G06F 1210

Patent

active

051796740

ABSTRACT:
A prediction logic device operating in conjunction with a vector processor to predict, before the completion of the translation of the virtual addresses of all of the data elements of a vector, the valid performance of all virtual-address to physical-address translations for the data elements of the vector. The prediction logic device asserts an MMOK signal to a scalar processor when it becomes known that no memory management fault and/or translation buffer miss will occur such that the scalar processor can resume vector instruction issue to the vector processor at the earliest possible time.

REFERENCES:
patent: 4620275 (1986-10-01), Wallach et al.
patent: 4811215 (1989-03-01), Smith
patent: 4926317 (1990-05-01), Wallach et al.
J. W. Plant et al., "Page boundary crossing detection hardware", IBM Technical Disclosure Bulletin, vol. 19, No. 1, Jun. 1976.

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