Method and apparatus for predicting floating-point exceptions

Details Method and apparatus for predicting floating-point exceptions Method and apparatus for predicting floating-point exceptions

1999-07-30

2003-10-07

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S505000

Reexamination Certificate

active

06631392

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is directed generally to a data processing apparatus having some form of parallel or pipelined architecture and including a floating-point unit, and more specifically to a method and apparatus for predicting floating-point exceptions.
2. Related Art
Computing apparatuses today, particularly those for scientific and engineering uses, perform many computations using “floating-point” numbers. One advantage of floating-point numbers is that they allow computations where the range of the magnitude of the numbers is very large, larger than can be handled, for example, with fixed point numbers (except with great difficulty). Floating-point representation of numbers corresponds very closely to what is often termed “scientific notation,” each being represented as the product of a normal number with a radix and an integer power of the radix. Thus, for example, a number might be represented as: 1.34700×10
8
. The number 1.34700 is called the significand or mantissa, the number 10 is called the radix, and the number 8 is called the exponent.
While floating-point numbers and floating-point computations provide significant advantages over fixed-point numbers and fixed-point computations, using floating-point numbers and floating-point computations involves the added complication of handling floating-point exceptions. ANSI/IEEE Standard 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, which is incorporated in its entirety herein by reference, lists five types of floating-point exception. These exceptions are: overflow, underflow, inexact, invalid operation, and divide by zero.
There exist today many well known methods and techniques for handling various floating-point exceptions; however, particular problems arise when floating-point computations are used in data processing systems capable of some form of parallel processing such as is found in pipelined architecture. A pipelined architecture usually encompasses processor designs in which multiple instructions are in various stages of execution, all at the same time.
When a floating-point instruction culminates in a floating-point exception, it is necessary to re-execute the instruction, but only after the operands are adjusted to avoid the exception occurring again. However, to re-execute the floating-point instruction, the data processing apparatus must be backed up, so to speak, which means that the results of any instructions executed, or partially executed, during the execution of the floating-point instruction must be saved until later, or thrown away. This, in turn, requires the state of the data processing apparatus to be returned to that originally encountered by the instruction.
The problem is exacerbated when different instructions require different execution times; that is, when certain instructions can be executed in two, four, or a small number of processor cycles of operation, whereas other instructions, particularly floating-point instructions, require many more processor cycles of operation to complete. In this case, a floating-point computation that results in an exception is more difficult to back out of. That is, it is more difficult to restore the state of the data processing apparatus to that originally encountered by the instruction in order to avoid the floating-point exception.
One simple solution to these problems would be to halt the processing of any subsequent instruction when a floating-point computation is first encountered, allowing only the floating-point computation to proceed. A check of the result can then be made to determine if an exception has occurred. If not, normal processing resumes. If an exception has occurred, the computation can be redone without having to flush the pipeline (i.e., to discard or store the results of the pipeline insofar as instructions following the floating-point instruction are concerned). The problem with this simple solution is that it can significantly degrade the performance of the data processing system.
What is, therefore, desired, is a method and apparatus for predicting floating-point exceptions for a given floating-point computation before the floating-point computation is actually executed. Predicting floating-point exceptions for a given floating-point computation means determining whether the given floating-point computation could potentially result in a floating-point exception. If a given floating-point computation is predicted to result in an exception (that is, there is a possibility that an exception could occur), then the processor will halt the processing of any subsequent instructions. Otherwise, subsequent instructions are processed normally. One such method and apparatus for predicting floating-point exceptions is described in U.S. Pat. No. 4,879,676 to Hansen, which is incorporated in its entirety herein by reference.
Given today's ever-growing demands for faster and more powerful computing apparatuses, particularly by the scientific and engineering communities, there exists a need for even more accurate prediction of floating-point exceptions. It is, therefore, desirable to improve upon the method and apparatus disclosed in the Hansen patent.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for the early prediction of whether floating-point exceptions could occur on data processing systems having floating-point units. Specifically, the method and apparatus of the present invention predict whether an overflow or underflow floating-point exception could occur as a result of a data processing system performing a particular floating-point add/subtract, multiply, multiply-add (Madd), or divide/square root operation. The invention makes its predictions based on at least one overflow threshold value, at least two underflow thresholds values (e.g., a first underflow threshold value and a second underflow threshold value), and a preliminary result exponent value that is derived from the values of the exponents of the floating-point numbers that are about to be acted upon by a data processing system.
An overflow or underflow exception prediction signal is generated by the present invention whenever the present invention predicts that an overflow or underflow exception could occur, respectively. The prediction signals generated by the present invention may be used by data processing system control units to temporarily halt any parallel processing operations that may be affected by an overflow or underflow floating-point exception prior to the exception actually occurring. To accomplish this feature, the present invention compares the value of a preliminary result exponent to the values of an overflow or underflow threshold. If the value of the preliminary result exponent is greater than or equal to the value of the overflow threshold, an overflow exception prediction signal is generated by an exception prediction unit. Similarly, if the value of the preliminary result exponent is less than the value of the underflow threshold to which it is compared, an underflow exception prediction signal is generated by an exception prediction unit.
An advantage of the present invention is that it is more accurate than prior methods in its predictions of floating-point exceptions, thereby improving the operational characteristics of data processing systems that employ the present invention. Additional features of this invention will become apparent from the following detailed description of the best mode for carrying out the invention and from the claims.


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