Method and apparatus for precharging match output in a cascaded

Details Method and apparatus for precharging match output in a cascaded Method and apparatus for precharging match output in a cascaded

1994-04-29

1997-04-15

Nelms, David C.

Static information storage and retrieval

Associative memories

Ferroelectric cell

36518907, 36518911, 365203, 326114, G11C 1504

Patent

active

056216777

ABSTRACT:
A method and apparatus for increasing the speed of a cascaded Content Addressable Memory (CAM) system by pre-charging the system match line of the CAM system are disclosed. The CAM system has (i) a plurality of CAM chips, (ii) a separate match output circuit for each CAM chip, (iii) a separate precharge circuit and pull-down circuit for each match output circuit and (iv) a system match line coupled to all of the match output circuits. Each of the precharge and pull-down circuits has an N-channel MOSFET. To increase the speed of the CAM system, the CAM system precharges the system match line so that the recovery time required for the system match line to change from a logic low to a logic high is minimized. Because each match output circuit has a precharge circuit, adding more CAM chips to the CAM system does not degrade the speed of the CAM system. The method for increasing the speed of the CAM system includes the steps of pre-charging the system match line, tri-stating the system match line and supplying a new match signal to its corresponding pull-down circuit.

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