Method and apparatus for pre-biasing inputs to a latching portio

Details Method and apparatus for pre-biasing inputs to a latching portio Method and apparatus for pre-biasing inputs to a latching portio

1998-05-13

1999-11-09

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

365203, G11C 706

Patent

active

059822023

ABSTRACT:
A method and apparatus for pre-biasing a sensing amplifier. A sense amp bias transistor connects a first latching transistor and a second latching transistor to ground while the sense amplifier is being precharged. The connection of the first latching transistor and the second latching transistor to ground through the sense amp bias transistor discharges any additional charge which may have built up on the inputs of the first latching transistor and the second latching transistor as a result of a Vbump condition. The sense amp bias transistor is enabled concurrently with the precharging of the sense amplifier. The sense amp bias transistor can be enabled by a controller, or alternatively, enablement is effectuated by inverting the signal which precharges the sense amplifier.

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patent: 5057718 (1991-10-01), Proebsting
patent: 5729159 (1998-03-01), Gersbach
Hirose, et al., "A 20-ns 4-Mb CMOS SRAM with Hierarchical Word Decoding Architecture", Oct. 5, 1990.

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