Method and apparatus for power-up state initialization in a data

Details Method and apparatus for power-up state initialization in a data Method and apparatus for power-up state initialization in a data

1994-02-04

1996-04-30

Harvey, Jack B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Converting, per se, of an ac input to corresponding dc at an...

327143, G06F 1300

Patent

active

055133584

ABSTRACT:
A method and apparatus for implementing a power-up state initialization. A power sense circuit provides a signal for indicating when the power supply, V.sub.DD, is of a voltage level greater than the minimum voltage level suitable for safely resolving CMOS logic. The power sense signal, when asserted, enables a small, on-chip ring oscillator. An output signal generated by the ring oscillator supplies a clocking signal to the clock drivers and to the clock state machine of the CPU, thereby providing internal clocks to a central processing unit (CPU). A counter counts the number of clock pulses provided to the CPU and disables the ring oscillator and the clock state machine (thereby stopping the internal data-processor clock drivers) when the accumulated number of clock pulses equals or exceeds a predefined number. The predefined number of internal clock pulses is the minimum number of clocks to process a reset condition that resolves all on-chip, CPU state conflicts and contention.

REFERENCES:
patent: 4736119 (1988-04-01), Chen et al.
patent: 5237699 (1993-08-01), Little et al.

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