Method and apparatus for power control in devices

Details Method and apparatus for power control in devices Method and apparatus for power control in devices

1993-05-21

1994-08-09

LaRoche, Eugene R.

Static information storage and retrieval

Powering

Conservation of power

365226, 365233, G11C 700

Patent

active

053372859

ABSTRACT:
A power control circuit to minimize power consumption of CMOS circuits by disabling/enabling the clock input to the CMOS circuit. A phase locked loop (PLL) or delay locked loop (DLL) drives a capacitive load of the component and a dummy load comparable to the component load. A standby latch is provided to control the clock input to the component. In a standby state, the clock signal is not provided to the component but the PLL/DLL continues to operate, driving the dummy load. Thus, when it is desirable to power on the circuit, the standby latch is reset and the clock signal is provided to the component, thereby turning on the component with little latency.

REFERENCES:
patent: 4937789 (1990-06-01), Matsubara
patent: 5113373 (1992-05-01), Lee
patent: 5193198 (1993-03-01), Yokouchi
patent: 5247655 (1993-09-01), Khan et al.

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