Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed
Reexamination Certificate
2002-05-20
2003-12-16
Thompson, Craig (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
Optical characteristic sensed
C438S401000, C438S462000, C257S798000, C356S625000
Reexamination Certificate
active
06664121
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to characterization of lithographic exposures and, more particularly, to measurement of relative position of marks or patterns formed by a lithographic tool, especially for analysis and possible correction and/or compensation of aberrations in the lithographic tool and/or precorrection of exposure patterns.
2. Description of the Prior Art
It has been recognized that formation of electrical elements (e.g. transistors, capacitors, interconnects and the like) of integrated circuits at smaller sizes and increased density provides benefits in both performance and functionality. Increased proximity of devices reduces signal propagation time and increases noise immunity while increased numbers of electrical elements on a chip of a given size allow increased circuit complexity and additional signal processing functions to be provided. Improved economy of manufacture also generally results from increased integration density since more electrical elements can be simultaneously formed by a given process.
While semiconductor device designs and the processes for their formation have become highly sophisticated in recent years and many self-aligned processes are known for forming various semiconductor structures at dimensions smaller than lithographic resolution, at least one lithographic process is required for the formation of any active or passive electrical element in order to define its location and its basic dimensions. A lithographic process includes the exposure of a resist with some form of energy (e.g. light, charged particles, x-rays, etc.) to which the resist is sensitive in a pattern which is subsequently developed to remove selected areas of the resist to allow processes to be selectively carried out where resist has been removed. Therefore, the quality of the exposure of the resist is of paramount importance to the formation of integrated circuits in accordance with a given design.
Various techniques are known and have been used to evaluate lithographic exposures and each has become substantially obsolete, in turn, as increased integration density and reduced size of electrical elements has required increased precision of measurement of a lithographically produced pattern. At the present time, the minimum feature size regimes of interest and the pattern fidelity which must be produced require an accuracy which exceeds that which can be achieved by direct inspection such as with an optical microscope. Further, the required image fidelity necessitates an extremely high degree of analysis and correction of the imaging capability or behavior of the imaging structure of the lithographic tool, particularly since features must be both properly sized and properly located throughout the lithographic exposure field. Aberrations cause changes in dimensions, shape and location of features of an intended pattern as a function of focus while flatness of the image field at the target is not assured.
Therefore, to obtain adequate pattern fidelity for fabrication of integrated circuits at current and foreseeable minimum feature size regimes requires capture of a large volume of data which must be analyzed to fully characterize and possibly correct aberrations in the behavior of the imaging structure of a lithographic tool. Not only is the required accuracy beyond that of known measurement techniques, as alluded to above, but the volume of data of such accuracy is far beyond the capacity of known techniques to capture in an economically acceptable amount of time. Further, it is desirable to not only capture and characterize the features produced in a lithographic resist by the imaging exposure but the actual features produced by lithographic processes performed in accordance with a patterned resist must also be adequately accurate. However, current and foreseeable minimum feature sizes are difficult if not impossible to resolve, much less measure using visible light. Accordingly, commonly applied image measurement techniques limit the density of integration which can be achieved.
Current designs of integrated circuits generally comprise many layers; a number of which may require one or more lithographic processes. For example, several metallization layers are usually applied in order to make connections to devices such as transistors formed on the chip, often through vias which must be formed by a lithographic exposure. In very densely integrated structures such as memories, it is also common to form a portion of the transistors or other devices using the connection, itself, such as the bit line or word line forming the gates of a plurality of transistors. In either case or other circumstances, the electrical properties of the devices may be severely affected by the alignment of a lithographic exposure with another, prior, exposure and structures formed in accordance therewith.
Such alignment, often referred to as “overlay”, is generally performed by manual adjustment using automated optical microscopes in accordance with alignment marks placed on the wafer in regions where chips are not formed. These marks generally must be relatively large in order to be easily observed and thus require valuable space on the chips and reducing the number of chips that can be manufactured from a single wafer. Further, the size of the marks limits the capture of appropriate information relevant to resolution and accuracy of the alignment process with respect to much smaller features and CDs. Thus, the alignment process, as currently performed, limits the uniformity of electrical properties of integrated circuits from wafer to wafer. Moreover, the overlay problem is compounded by aberrations in the exposure and substantially correct alignment a one or more locations on the wafer does not guarantee proper alignment across the entire exposure field particularly when the alignment or registration marks are located a substantial distance from the elements on the chips, as is generally the current practice.
Additionally, the size of the alignment marks are generally not comparable to the size of features to be formed and there is, for that reason, no assurance that the overlay alignment will be of sufficient accuracy or resolution to properly form the devices in the design. In a broader sense, the optimum performance of a lithographic exposure tool or process cannot realistically be achieved using metrology features which are not of comparable dimensions and spacings to the features of the integrated circuit design to be produced.
SUMMARY OF THE INVENTION
To extend position measurement capability to support, for example, manufacture of current and foreseeable integrated circuit designs, the invention provides a measurement technique and apparatus for measurement of relative location of extremely fine and potentially closely spaced features of critical dimensions corresponding to minimum feature size regimes of interest produced by a lithographic exposure tool.
Further, the invention provides a technique and apparatus for characterization of the performance of a lithographic exposure tool and the true performance of an overall lithographic process using features comparable dimensions to a given integrated circuit design. The invention can also be applied to automate and increase accuracy of overlay processes for multiple lithographic exposures and processes at resolution equal to that required for any given integrated circuit design at any minimum feature size regime. By doing so, the invention also supports an overlay accuracy of a very small fraction of the minimum feature size such that wafer to wafer and chip to chip variation in electrical properties of individual elements of the integrated circuit can be avoided, while reducing the chip space required for alignment or registration marks and even the current practice of placement on scribe or dicing lines, where possible, that are close to the elements to be formed and effectively require no wafer space since only portions of the wafer consumed when chips are separated
Grodnensky Ilya
Slonaker Steve
Nikon Precision Inc.
Thompson Craig
Whitham, Curtis & Christofferson, PLC.
LandOfFree
Method and apparatus for position measurement of a pattern... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for position measurement of a pattern..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for position measurement of a pattern... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3168594