Abrading – Precision device or process - or with condition responsive... – By optical sensor
Reexamination Certificate
2001-10-10
2004-11-30
Morgan, Eileen P. (Department: 3723)
Abrading
Precision device or process - or with condition responsive...
By optical sensor
C451S010000, C451S011000, C451S044000
Reexamination Certificate
active
06824446
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to fabrication of integrated circuits, and more particularly, to a method and apparatus for directly polishing an outer edge ring of a semiconductor wafer to prevent delamination of layers of material deposited on the outer edge ring of the semiconductor wafer during fabrication of integrated circuits thereon.
BACKGROUND OF THE INVENTION
FIG. 1
shows a typical shape of a semiconductor wafer
102
having integrated circuits fabricated thereon, as known to one of ordinary skill in the art of integrated circuit fabrication. During fabrication of integrated circuits on the semiconductor wafer
102
, various layers of material are deposited onto the semiconductor wafer
102
on top of one another, as known to one of ordinary skill in the art of integrated circuit fabrication. Such layers of material however may delaminate and peel-off away from near the outer edge
103
of the semiconductor wafer
102
, as known to one of ordinary skill in the art of integrated circuit fabrication. Such peeling of material away from near the outer edge
103
of the semiconductor wafer
102
creates a source of contaminants for the rest of the semiconductor wafer
102
which may render the integrated circuits fabricated on the semiconductor wafer inoperative.
A factor which may promote this undesired delamination and peeling off of layers of material away from near the outer edge
103
of the semiconductor wafer
102
are clamps which hold the semiconductor wafer
102
near the outer edge
103
of the semiconductor wafer
102
. The semiconductor wafer
102
is held by clamping mechanisms within various integrated circuit fabrication equipment near the outer edge
103
of the semiconductor wafer
102
.
Referring to
FIG. 2A
for example, a clamping ring
104
may hold the semiconductor wafer
102
all around the outer edge of the semiconductor wafer
102
. (The dashed circle in
FIG. 2A
represents the circumference of the semiconductor wafer
102
held by the clamping ring
104
.)
FIG. 2B
is the cross-sectional view of the clamping ring
104
holding the semiconductor wafer
102
across line I—I in FIG.
2
A. Referring to
FIG. 2B
, the clamping ring
104
holds and covers an outer edge ring
106
all around the circumference of the semiconductor wafer
102
.
Alternatively, referring to
FIG. 3A
, a plurality of clamping pins, including a first clamping pin
302
, a second clamping pin
304
, a third clamping pin
306
, and a fourth clamping pin
308
holds the semiconductor wafer
102
at a plurality of positions near the outer edge of the semiconductor wafer
102
. Typically, a higher number of clamping pins holds the semiconductor wafer
102
near the outer edge
103
of the semiconductor wafer
102
, but four clamping pins
302
,
304
,
306
, and
308
are shown in
FIG. 3A
for clarity of illustration.
FIG. 3B
is the cross-sectional view of the clamping pins
302
and
306
holding the semiconductor wafer
102
across line II—II in FIG.
3
A. Referring to
FIG. 3B
, the clamping pins
302
and
306
hold and cover an outer edge distance
310
of the semiconductor wafer
102
.
When either of the clamping ring
104
of
FIG. 2A
or the clamping pins
302
,
304
,
306
, and
308
of
FIG. 3A
holds the semiconductor wafer
102
during deposition of material on the semiconductor wafer, such material is not deposited near the outer edge of the semiconductor wafer
102
held by the clamping ring
104
or the clamping pins
302
,
304
,
306
, and
308
. The semiconductor wafer
102
moves through multiple integrated circuit fabrication equipments typically for deposition of numerous layers of material. Because of misalignment of the semiconductor wafer
102
at the various integrated circuit fabrication equipments, these layers of material may delaminate and peel-off away from near the edge of the semiconductor wafer.
Referring to
FIG. 4
for example, a first layer of material
402
is deposited on the semiconductor wafer
102
at a first integrated circuit fabrication equipment, a second layer of material
404
is deposited at a second integrated circuit fabrication equipment, and a third layer of material
406
is deposited at a third integrated circuit fabrication equipment. At each of many of these different integrated circuit fabrication equipments, a clamping ring or a plurality of clamping pins should hold the semiconductor wafer
102
at an outer edge distance
408
inward from the outer edge
103
of the semiconductor wafer.
Such an outer edge distance
408
is typically on the order of 4 mm (millimeters). Because of such a short distance and because the many fabrication equipments lack fine wafer alignment capability with respect to the clamping ring or the plurality of clamping pins, the misalignment of the semiconductor wafer
104
through the multiple integrated circuit fabrication equipments results in various extensions of the layers of materials into the outer edge distance
408
.
Referring to
FIG. 4
, for example, the first layer of material
402
extends outward toward the outer edge
103
of the semiconductor wafer
102
beyond the outer edge distance
408
. The second layer of material
404
extends outward even further than the first layer of material
402
toward the outer edge
103
of the semiconductor wafer beyond the outer edge distance
408
. The third layer of material
406
is misaligned such that the third layer of material
406
extends inward toward the center of the semiconductor wafer
102
away from the outer edge distance
408
.
Because of such misalignment of the multiple layers of material
402
,
404
, and
406
, any of such layer of material
402
,
404
, and
406
may delaminate and peel-off away from near the outer edge
103
of the semiconductor wafer
102
, as known to one of ordinary skill in the art of integrated circuit fabrication. For example, referring to
FIG. 4
, the second layer of material
404
hangs over the first layer of material
402
and beyond the third layer of material
406
. Thus, the second layer of material
404
is likely to peel-off away from the semiconductor wafer
102
. Such delamination and peeling-off of the misaligned layers of material are especially likely when abutting layers of material do not have strong adhesion.
Such peeling of material away from the edge of the semiconductor wafer may render the integrated circuits thereon inoperative. In addition, such peeling of material away from near the outer edge
103
of the semiconductor wafer
102
creates a source of contaminants for the rest of the semiconductor wafer
102
which may render the integrated circuits fabricated thereon inoperative. Such peeling of material away from near the outer edge
103
of the semiconductor wafer
102
may also contaminate integrated circuit fabrication equipment chambers during subsequent process steps. In the prior art, when a layer of material begins to peel away from the semiconductor wafer, the semiconductor wafer is reworked to remove the layer of material that is peeling away. However, such reworking of the semiconductor wafer is relatively complicated and time-consuming or in some cases very difficult. Alternatively, such a semiconductor wafer is scrapped which is a waste. Thus, a mechanism is desired for polishing the misaligned layers of material near the outer edge of the semiconductor wafer to efficiently and effectively prevent the delamination and peeling-off of the layers of material away from the semiconductor wafer during fabrication of integrated circuits thereon.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, in an apparatus and method for polishing an outer edge ring of a semiconductor wafer, the semiconductor wafer is mounted on a wafer chuck. The semiconductor wafer has layers of material deposited thereon during fabrication of integrated circuits on the semiconductor wafer. The wafer chuck holding the semiconductor wafer is rotated such that the semiconductor wafer rotates. A polishing pad is moved toward the semicon
Ang Boon Yong
Harris Kenneth R.
Advanced Micro Devices , Inc.
Choi Monica H.
Morgan Eileen P.
LandOfFree
Method and apparatus for polishing an outer edge ring on a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for polishing an outer edge ring on a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for polishing an outer edge ring on a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3354888