Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
2000-05-17
2002-10-08
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C331S025000, C331S034000, C331S057000, C331S17700V, C327S270000, C327S272000, C327S288000, C327S290000
Reexamination Certificate
active
06462623
ABSTRACT:
FIELD OF THE INVENTION
The field of the invention relates to Phase Lock Loop (PLL) design and; more specifically, to reducing jitter in the output of a voltage controlled oscillator.
BACKGROUND
Phase Lock Loop (PLL) designs are commonly used to synchronize the output of an oscillator with a reference clock. Synchronization means a reference clock (Ref_Clock) signal and an oscillator output (Ref_Clock×N) signal operate at a fixed frequency and phase relationship. The oscillator output appears as a multiple (“N”) of the reference clock having a frequency of N·fo (where fo is the frequency of the reference clock).
FIG. 1
shows a general approach. In
FIG. 1
, the oscillator
101
is a voltage controlled oscillator (VCO) that produces a signal output having a frequency proportional to the voltage placed at its input
101
a
. The frequency of the oscillator
101
is downconverted in the feedback loop by the downconverter
102
. The downconverter
102
is typically a counter that triggers an edge at its output signal only after “N” edges are observed in the VCO
101
output. Downconverter
102
allows the VCO
101
to operate at a higher frequency than the reference clock (Ref_Clock).
Phase comparator
103
produces an output based upon the phase difference between the downconverter
102
output signal and the reference clock. In the particular approach shown in
FIG. 1
, a stream of pulses appear on the “upn” signal if the phase of the downconverter
102
output signal lags behind the reference clock. The width of the pulses within “upn” pulse stream are proportional to the amount of lag that exists. Similarly, a stream of pulses appear on the “down” signal if the phase of the downconverter
102
output signal is ahead of (i.e., “leads”) the reference clock. The width of the pulses within the “down” pulse stream are proportional to the amount of lead that exists.
If a pulse stream appears on the “upn” signal, pulses of current are supplied by charge pump
104
to the loop filter
105
. This raises the voltage at the VCO
101
input since loop filter
105
acts as an integrator. Raising the voltage at the VCO
101
input increases the frequency of the VCO
101
output signal. Similarly, if a pulse stream appears on the “down” signal, pulses of current are pulled by charge pump
104
from the loop filter
105
which lowers the voltage at the VCO
101
input. Lowering the voltage at the VCO
101
input decreases the frequency of the VCO
101
output signal. Note that loop
101
,
105
should also have adequate phase margin such that phase detector
103
does not confuse the proper output signaling (e.g., sending a “down” signal when the downconverter
102
output signal actually lags the reference clock).
During an initial synchronization time, the voltage at the VCO
101
input approaches its proper value (i.e., the voltage corresponding to the proper VCO output frequency) as a result of the charge pump's activity. During this time, the charge pump usually supplies and/or pulls current to/from the loop filter
105
linearly with the aforementioned pulse streams. As the voltage at the VCO
101
approaches the proper value, the width of the current pulses from the charge pump
104
narrow. Ideally, when the proper VCO
101
input voltage is eventually reached, the phase detector
103
does not recognize any error and does not submit any pulse streams to the charge pump. At this point, the PLL is stabilized and the voltage at the VCO
101
input remains substantially constant.
Since the dynamic activity of the charge pump
103
in relation to the design of the loop filter
105
determines the proper voltage at the VCO
101
input, the small signal transfer characteristics of the loop filter
105
are of noteworthy concern in PLL applications. For example, in order to increase the frequency at the VCO
101
output for a given reference clock frequency (or, alternatively, to keep the frequency of the VCO constant while reducing the speed of the reference clock), the division factor “N” associated with the downconverter
102
may be increased.
If N is increased to move the VCO output frequency up, the gain of the VCO (given in Hz/volt) should be increased so that the voltage presented by the loop filter
105
may be used to give an even higher output frequency. If N is increased to move the reference clock frequency down while keeping the VCO output frequency the same, the frequencies associated with the current pulses used to pump the loop filter
105
shift more toward 0.0 Hz lower in the spectrum. In either case, the problem arises that the PLL is more susceptible to jitter produced by small fluctuations in the voltage presented at the VCO
101
input. In the former case, the VCO is more sensitive to voltage fluctuations because it has been designed with a higher gain; in the later case the frequencies associated with the current pulse streams are closer to the passband of the filter (resulting in less attenuation of these time varying signals and correspondingly more fluctuation at the VCO
101
input).
SUMMARY OF INVENTION
An apparatus is described comprising a current source and a pair of transistors coupled to the current source. A pair of variable loads are coupled to the pair of transistors such that a first of the pair of transistors drives a first of the pair of variable loads and a second of the pair of transistors drives a second of the pair of variable loads. Each of the pair of variable loads are coupled to a high gain input and a low gain input. Another apparatus is described comprising an oscillator having a high gain input and a low gain input. The oscillator comprises a series of inverters where each inverter output is coupled to the next inverter input in the series. At least one of the inverters comprises a current source and a pair of transistors coupled to the current source. A pair of variable loads are coupled to the pair of transistors such that a first of the pair of transistors drives a first of the pair of variable loads and a second of the pair of transistors drives a second of the pair of variable loads. Each of the pair of variable loads are coupled to a high gain input and a low gain input.
Yet another apparatus is described comprising an oscillator having a high gain input and a low gain input. The oscillator comprises a series of inverters, each inverter output is coupled to the next inverter input in the series. The low gain input is coupled to less than all of the inverters within the series.
A phase lock loop is also described comprising an on chip oscillator. An on chip loop filter is coupled to the on chip oscillator. The on chip loop filter comprises only components that are on chip and one of the components is an on chip resistor. An on chip switch is coupled to the on chip resistor. An on chip circuit is coupled to the on chip switch and the on chip circuit is configured to modulate the on chip switch at a duty cycle.
Another apparatus is described comprising an oscillator having a first and second inputs. A first filter has an output coupled to the first oscillator input. A second filter has an output coupled to the second oscillator input and the first filter input. Isolation is coupled between the second filter output and the first filter input.
A method is also described comprising passing a signal representative of the phase difference between two signals through a loop filter. The loop filter has an on chip resistor. A switch placed in series with the on chip resistor is modulated at a duty cycle to increase the effective resistance of the on chip resistor. The output of the loop filter is passed to a voltage controlled oscillator. Another method is described comprising presenting a high gain signal and a low gain signal to a variable load within an inverter. The inverter has a delay that increases with the impedance of the variable load. The variable load impedance is changed in response to the high gain signal. The variable load impedance is changed in response to the low gain signal such that a greater change in impedance is c
Foley David J.
Horan John M.
Ryan John G.
Smyth Mark M.
Blakely , Sokoloff, Taylor & Zafman LLP
Mis David
Parthus Ireland Limited
LandOfFree
Method and apparatus for PLL with improved jitter performance does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for PLL with improved jitter performance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for PLL with improved jitter performance will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2998891